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u-boot/arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi

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ARM: dts: stm32: Fix AV96 and DHCOR split The commit 132e5b68986d ("ARM: dts: stm32: Split AV96 into DHCOR SoM and AV96 board") was not applied correctly and in full, and omitted an important split of the SoM into 3V3 and 1V8 options. The Avenger96 board is based on the 1V8 IO option of the DHCOR SoM, however this is an optional modification of the 3V3 IO DHCOR SoM with extra on-SoM regulator to cater for the 96boards 1V8 IO requirements. Reinstate the split between the 1V8 and 3V3 IO variants. Fixes: 132e5b68986d ("ARM: dts: stm32: Split AV96 into DHCOR SoM and AV96 board") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-04-27 11:16:02 +00:00
// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
/*
ARM: dts: stm32: Synchronize DHCOR DTs with Linux 5.15.12 Synchronize DH DHCOR DTs with Linux commit 25960cafa06e ("Linux 5.15.12"). There is no functional change to the resulting DTs. The eeprom0 alias is now reinstated in SoM u-boot dtsi, the PHY reset GPIO is reinstated in AV96 u-boot dtsi. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-12-30 22:46:46 +00:00
* Copyright (C) Linaro Ltd 2019 - All Rights Reserved
* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
ARM: dts: stm32: Fix AV96 and DHCOR split The commit 132e5b68986d ("ARM: dts: stm32: Split AV96 into DHCOR SoM and AV96 board") was not applied correctly and in full, and omitted an important split of the SoM into 3V3 and 1V8 options. The Avenger96 board is based on the 1V8 IO option of the DHCOR SoM, however this is an optional modification of the 3V3 IO DHCOR SoM with extra on-SoM regulator to cater for the 96boards 1V8 IO requirements. Reinstate the split between the 1V8 and 3V3 IO variants. Fixes: 132e5b68986d ("ARM: dts: stm32: Split AV96 into DHCOR SoM and AV96 board") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-04-27 11:16:02 +00:00
* Copyright (C) 2020 Marek Vasut <marex@denx.de>
*/
/ {
ARM: dts: stm32: Synchronize DHCOR DTs with Linux 5.15.12 Synchronize DH DHCOR DTs with Linux commit 25960cafa06e ("Linux 5.15.12"). There is no functional change to the resulting DTs. The eeprom0 alias is now reinstated in SoM u-boot dtsi, the PHY reset GPIO is reinstated in AV96 u-boot dtsi. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-12-30 22:46:46 +00:00
/* Enpirion EP3A8LQI U2 on the DHCOR */
ARM: dts: stm32: Fix AV96 and DHCOR split The commit 132e5b68986d ("ARM: dts: stm32: Split AV96 into DHCOR SoM and AV96 board") was not applied correctly and in full, and omitted an important split of the SoM into 3V3 and 1V8 options. The Avenger96 board is based on the 1V8 IO option of the DHCOR SoM, however this is an optional modification of the 3V3 IO DHCOR SoM with extra on-SoM regulator to cater for the 96boards 1V8 IO requirements. Reinstate the split between the 1V8 and 3V3 IO variants. Fixes: 132e5b68986d ("ARM: dts: stm32: Split AV96 into DHCOR SoM and AV96 board") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-04-27 11:16:02 +00:00
vdd_io: regulator-buck-io {
compatible = "regulator-fixed";
regulator-name = "buck-io";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vdd>;
};
};
ARM: dts: stm32: Move DHCOR BUCK3 VDD 2V9 adjustment to 1V8 DTSI The Buck3 on DHCOR is used to supply IO voltage. It can output either 3V3 in the default DHCOR configuration, or 2V9 in case of AV96 DHCOR variant which has extra Empirion DCDC converter in front of the 1V8 IO supply, or outright 1V8 in case of 1V8 IO DHCOR without the Empirion DCDC converter. The 2V9 mode in case of AV96 DHCOR variant is used to reduce unnecessarily high input voltage to the Empirion DCDC converter, so move it into matching DTSI to stop confusing users. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-04 12:50:04 +00:00
&vdd {
ARM: dts: stm32: Configure Buck3 voltage per PMIC NVM on Avenger96 The Avenger96 board comes in multiple regulator configurations. - rev.100 or rev.200 have Buck3 preconfigured to 3V3 operation on boot and contains extra Enpirion EP53A8LQI DCDC converter which supplies the IO. Reduce Buck3 voltage to 2V9 to not waste power. - rev.200L have Buck3 preconfigured to 1V8 operation and have no Enpirion EP53A8LQI DCDC anymore, the IO is supplied from Buck3. Configure the Buck3 voltage on this board per PMIC NVM settings and update buck3 voltage limits in DT passed to OS before booting OS to prevent potential hardware damage. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-05-11 21:09:33 +00:00
regulator-min-microvolt = <1800000>;
ARM: dts: stm32: Move DHCOR BUCK3 VDD 2V9 adjustment to 1V8 DTSI The Buck3 on DHCOR is used to supply IO voltage. It can output either 3V3 in the default DHCOR configuration, or 2V9 in case of AV96 DHCOR variant which has extra Empirion DCDC converter in front of the 1V8 IO supply, or outright 1V8 in case of 1V8 IO DHCOR without the Empirion DCDC converter. The 2V9 mode in case of AV96 DHCOR variant is used to reduce unnecessarily high input voltage to the Empirion DCDC converter, so move it into matching DTSI to stop confusing users. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-04 12:50:04 +00:00
regulator-max-microvolt = <2900000>;
};
ARM: dts: stm32: Fix AV96 and DHCOR split The commit 132e5b68986d ("ARM: dts: stm32: Split AV96 into DHCOR SoM and AV96 board") was not applied correctly and in full, and omitted an important split of the SoM into 3V3 and 1V8 options. The Avenger96 board is based on the 1V8 IO option of the DHCOR SoM, however this is an optional modification of the 3V3 IO DHCOR SoM with extra on-SoM regulator to cater for the 96boards 1V8 IO requirements. Reinstate the split between the 1V8 and 3V3 IO variants. Fixes: 132e5b68986d ("ARM: dts: stm32: Split AV96 into DHCOR SoM and AV96 board") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-04-27 11:16:02 +00:00
&pwr_regulators {
vdd-supply = <&vdd_io>;
};
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