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u-boot/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi

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arm: dts: ls1028a: define QDS networking protocol combinations Includes DT definition for the following serdes protocols using various PHY cards: 85xx, 13xx, 65xx, 9999, 7777. Note that the default device tree for QDS now uses 85xx. Enabling any of the others requires patching the fsl-ls1028a-qds.dtsi file (the includes at the bottom of the file). The phy-handle is specified as a path rather than a label because it is possible to use the #include multiple times (meaning that more than one PHY riser card of one type is inserted), and therefore, there would be duplicate labels with the same name. LBRW means that the board needs lane B rework before using this dtsi. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-01-27 11:00:00 +00:00
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LS1028A-QDS device tree fragment for RCW 1xxx
*
net: update NXP copyright text NXP Legal insists that the following are not fine: - Saying "NXP Semiconductors" instead of "NXP", since the company's registered name is "NXP" - Putting a "(c)" sign in the copyright string - Putting a comma in the copyright string The only accepted copyright string format is "Copyright <year-range> NXP". This patch changes the copyright headers in the networking files that were sent by me, or derived from code sent by me. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-09-17 11:27:13 +00:00
* Copyright 2019-2021 NXP
arm: dts: ls1028a: define QDS networking protocol combinations Includes DT definition for the following serdes protocols using various PHY cards: 85xx, 13xx, 65xx, 9999, 7777. Note that the default device tree for QDS now uses 85xx. Enabling any of the others requires patching the fsl-ls1028a-qds.dtsi file (the includes at the bottom of the file). The phy-handle is specified as a path rather than a label because it is possible to use the #include multiple times (meaning that more than one PHY riser card of one type is inserted), and therefore, there would be duplicate labels with the same name. LBRW means that the board needs lane B rework before using this dtsi. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-01-27 11:00:00 +00:00
*/
/*
* This setup is using a SCH-30842 card with AQR112 PHY in slot 1 for ENETC
* port 0 USXGMII.
*/
&slot1 {
#include "fsl-sch-30842.dtsi"
};
arm: dts: ls1028a: update the labels Update the labels of the nodes to match the kernel ones. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-10-13 16:14:15 +00:00
&enetc_port0 {
arm: dts: ls1028a: define QDS networking protocol combinations Includes DT definition for the following serdes protocols using various PHY cards: 85xx, 13xx, 65xx, 9999, 7777. Note that the default device tree for QDS now uses 85xx. Enabling any of the others requires patching the fsl-ls1028a-qds.dtsi file (the includes at the bottom of the file). The phy-handle is specified as a path rather than a label because it is possible to use the #include multiple times (meaning that more than one PHY riser card of one type is inserted), and therefore, there would be duplicate labels with the same name. LBRW means that the board needs lane B rework before using this dtsi. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-01-27 11:00:00 +00:00
status = "okay";
arm: dts: ls1028a-qds: declare in-band autoneg for Ethernet ports The commit in the Fixes: tag below broke traffic through switch ports where the SERDES protocol requires in-band autoneg and this requirement isn't described in the device tree: SGMII, QSGMII, USXGMII (with 2500Base-X, in-band autoneg isn't supported). The LS1028A-QDS boards are not yet ready for syncing their device trees with Linux, since Ethernet is missing there (but has been submitted): https://lore.kernel.org/lkml/20211112223457.10599-11-leoyang.li@nxp.com/ When agreement is reached for the Ethernet support in Linux, there will be a sync for these boards as well. For now, just enable in-band autoneg to fix the breakage. Fixes: e3789a726269 ("net: dsa: felix: configure the in-band autoneg property based on OF node info") Cc: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-01-03 12:47:37 +00:00
managed = "in-band-status";
arm: dts: ls1028a: define QDS networking protocol combinations Includes DT definition for the following serdes protocols using various PHY cards: 85xx, 13xx, 65xx, 9999, 7777. Note that the default device tree for QDS now uses 85xx. Enabling any of the others requires patching the fsl-ls1028a-qds.dtsi file (the includes at the bottom of the file). The phy-handle is specified as a path rather than a label because it is possible to use the #include multiple times (meaning that more than one PHY riser card of one type is inserted), and therefore, there would be duplicate labels with the same name. LBRW means that the board needs lane B rework before using this dtsi. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-01-27 11:00:00 +00:00
phy-mode = "usxgmii";
arm: dts: ls1028a: move I2C controller nodes into /soc While inserting them into the new location, keep them sorted by the register base offset just like in the linux kernel device tree. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-10-13 16:14:05 +00:00
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
arm: dts: ls1028a: define QDS networking protocol combinations Includes DT definition for the following serdes protocols using various PHY cards: 85xx, 13xx, 65xx, 9999, 7777. Note that the default device tree for QDS now uses 85xx. Enabling any of the others requires patching the fsl-ls1028a-qds.dtsi file (the includes at the bottom of the file). The phy-handle is specified as a path rather than a label because it is possible to use the #include multiple times (meaning that more than one PHY riser card of one type is inserted), and therefore, there would be duplicate labels with the same name. LBRW means that the board needs lane B rework before using this dtsi. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-01-27 11:00:00 +00:00
};
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