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u-boot/arch/arm/mach-stm32mp/Kconfig.15x

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arm: stm32mp: add sub config Kconfig.15x Add sub Kconfig for each SOC in the STM32 CPU family. It is a preliminary step to introduce a new SOC in the STM32MP family. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-20 16:24:44 +00:00
if STM32MP15x
config STM32MP15x_STM32IMAGE
bool "Support STM32 image for generated U-Boot image"
depends on TFABOOT
help
Support of STM32 image generation for SOC STM32MP15x
for TF-A boot when FIP container is not used
choice
prompt "STM32MP15x board select"
optional
config TARGET_ST_STM32MP15x
bool "STMicroelectronics STM32MP15x boards"
imply BOOTSTAGE
imply CMD_BOOTSTAGE
imply CMD_CLS if CMD_BMP
imply DISABLE_CONSOLE
imply PRE_CONSOLE_BUFFER
imply SILENT_CONSOLE
help
target the STMicroelectronics board with SOC STM32MP15x
managed by board/st/stm32mp1:
Evalulation board (EV1) or Discovery board (DK1 and DK2).
The difference between board are managed with devicetree
config TARGET_DH_STM32MP1_PDK2
bool "DH STM32MP1 PDK2"
help
Target the DH PDK2 development kit with STM32MP15x SoM.
config TARGET_MICROGEA_STM32MP1
bool "Engicam MicroGEA STM32MP1 SOM"
imply BOOTSTAGE
imply CMD_BOOTSTAGE
imply CMD_CLS if CMD_BMP
imply DISABLE_CONSOLE
imply PRE_CONSOLE_BUFFER
imply SILENT_CONSOLE
help
MicroGEA STM32MP1 is a STM32MP157A based Micro SOM.
MicroGEA STM32MP1 MicroDev 2.0:
* MicroDev 2.0 is a general purpose miniature carrier board with CAN,
LTE and LVDS panel interfaces.
* MicroGEA STM32MP1 needs to mount on top of this MicroDev 2.0 board
for creating complete MicroGEA STM32MP1 MicroDev 2.0 Carrier board.
MicroGEA STM32MP1 MicroDev 2.0 7" OF:
* 7" OF is a capacitive touch 7" Open Frame panel solutions with LVDS
panel and toucscreen.
* MicroGEA STM32MP1 needs to mount on top of MicroDev 2.0 board with
pluged 7" OF for creating complete MicroGEA STM32MP1 MicroDev 2.0 7"
Open Frame Solution board.
config TARGET_ICORE_STM32MP1
bool "Engicam i.Core STM32MP1 SOM"
imply BOOTSTAGE
imply CMD_BOOTSTAGE
imply CMD_CLS if CMD_BMP
imply DISABLE_CONSOLE
imply PRE_CONSOLE_BUFFER
imply SILENT_CONSOLE
help
i.Core STM32MP1 is an EDIMM SOM based on STM32MP157A.
i.Core STM32MP1 EDIMM2.2:
* EDIMM2.2 is a Form Factor Capacitive Evaluation Board.
* i.Core STM32MP1 needs to mount on top of EDIMM2.2 for
creating complete i.Core STM32MP1 EDIMM2.2 Starter Kit.
i.Core STM32MP1 C.TOUCH 2.0
* C.TOUCH 2.0 is a general purpose Carrier board.
* i.Core STM32MP1 needs to mount on top of this Carrier board
for creating complete i.Core STM32MP1 C.TOUCH 2.0 board.
endchoice
arm: stm32mp: add CONFIG_STM32MP15_PWR Add config CONFIG_STM32MP15_PWR to handle the access to regulators managed by the PWR driver defined in pwr_regulator.c This driver is only used in U-Boot by STM32MP15x family. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-20 16:24:45 +00:00
config STM32MP15_PWR
bool "Enable driver for STM32MP15x PWR"
depends on DM_REGULATOR && DM_PMIC
default y
help
This config enables implementation of driver-model pmic and
regulator uclass features for access to STM32MP15x PWR.
config SPL_STM32MP15_PWR
bool "Enable driver for STM32MP15x PWR in SPL"
depends on SPL && SPL_DM_REGULATOR && SPL_DM_PMIC
default y
help
This config enables implementation of driver-model pmic and
regulator uclass features for access to STM32MP15x PWR in SPL.
Rename CONFIG_SYS_TEXT_BASE to CONFIG_TEXT_BASE The current name is inconsistent with SPL which uses CONFIG_SPL_TEXT_BASE and this makes it imposible to use CONFIG_VAL(). Rename it to resolve this problem. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-10-21 00:22:39 +00:00
config TEXT_BASE
arm: stm32mp: add sub config Kconfig.15x Add sub Kconfig for each SOC in the STM32 CPU family. It is a preliminary step to introduce a new SOC in the STM32MP family. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-20 16:24:44 +00:00
default 0xC0100000
config PRE_CON_BUF_ADDR
default 0xC02FF000
config PRE_CON_BUF_SZ
default 4096
config BOOTSTAGE_STASH_ADDR
default 0xC3000000
if BOOTCOUNT_GENERIC
config SYS_BOOTCOUNT_SINGLEWORD
default y
# TAMP_BOOTCOUNT = TAMP_BACKUP_REGISTER(21)
config SYS_BOOTCOUNT_ADDR
default 0x5C00A154
endif
if DEBUG_UART
config DEBUG_UART_BOARD_INIT
stm32mp: fix compilation issue with DEBUG_UART Fix the compilation issue when CONFIG_DEBUG_UART is activated drivers/serial/serial_stm32.o: in function `debug_uart_init': drivers/serial/serial_stm32.c:291: undefined reference to \ `board_debug_uart_init' The board_debug_uart_init is needed for SPL boot, called in cpu.c::mach_cpu_init(); it is defined in board/st/stm32mp1/spl.c. But with the removal #ifdefs patch, the function debug_uart_init() is always compiled even if not present in the final U-Boot image. This patch adds a file to provided this function when DEBUG_UART and SPL are activated. Fixes: c8b2eef52b6c ("stm32mp15: tidy up #ifdefs in cpu.c") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-10-11 14:44:26 +00:00
default y if SPL
arm: stm32mp: add sub config Kconfig.15x Add sub Kconfig for each SOC in the STM32 CPU family. It is a preliminary step to introduce a new SOC in the STM32MP family. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-20 16:24:44 +00:00
# debug on UART4 by default
config DEBUG_UART_BASE
default 0x40010000
# clock source is HSI on reset
config DEBUG_UART_CLOCK
default 64000000
endif
source "board/st/stm32mp1/Kconfig"
source "board/dhelectronics/dh_stm32mp1/Kconfig"
source "board/engicam/stm32mp1/Kconfig"
endif
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