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u-boot/arch/arm/include/asm/arch-aspeed/wdt.h

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SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
/* SPDX-License-Identifier: GPL-2.0+ */
aspeed: Add drivers common to all Aspeed SoCs Add support for Watchdog Timer, which is compatible with AST2400 and AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver does not follow the driver model. It also uses fixed clock, so no clock driver is needed. Add support for timer for Aspeed ast2400/ast2500 devices. The driver actually controls several devices, but because all devices share the same Control Register, it is somewhat difficult to completely decouple them. Since only one timer is needed at the moment, this should be OK. The timer uses fixed clock, so does not rely on a clock driver. Add sysreset driver, which uses watchdog timer to do resets and particular watchdog device to use is hardcoded (0) Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-18 21:44:55 +00:00
/*
* (C) Copyright 2016 Google, Inc
*/
#ifndef _ASM_ARCH_WDT_H
#define _ASM_ARCH_WDT_H
#define WDT_BASE 0x1e785000
/*
* Special value that needs to be written to counter_restart register to
* (re)start the timer
*/
#define WDT_COUNTER_RESTART_VAL 0x4755
/* Control register */
#define WDT_CTRL_RESET_MODE_SHIFT 5
#define WDT_CTRL_RESET_MODE_MASK 3
#define WDT_CTRL_EN (1 << 0)
#define WDT_CTRL_RESET (1 << 1)
#define WDT_CTRL_CLK1MHZ (1 << 4)
#define WDT_CTRL_2ND_BOOT (1 << 7)
/* Values for Reset Mode */
#define WDT_CTRL_RESET_SOC 0
#define WDT_CTRL_RESET_CHIP 1
#define WDT_CTRL_RESET_CPU 2
#define WDT_CTRL_RESET_MASK 3
/* Reset Mask register */
#define WDT_RESET_ARM (1 << 0)
#define WDT_RESET_COPROC (1 << 1)
#define WDT_RESET_SDRAM (1 << 2)
#define WDT_RESET_AHB (1 << 3)
#define WDT_RESET_I2C (1 << 4)
#define WDT_RESET_MAC1 (1 << 5)
#define WDT_RESET_MAC2 (1 << 6)
#define WDT_RESET_GCRT (1 << 7)
#define WDT_RESET_USB20 (1 << 8)
#define WDT_RESET_USB11_HOST (1 << 9)
#define WDT_RESET_USB11_EHCI2 (1 << 10)
#define WDT_RESET_VIDEO (1 << 11)
#define WDT_RESET_HAC (1 << 12)
#define WDT_RESET_LPC (1 << 13)
#define WDT_RESET_SDSDIO (1 << 14)
#define WDT_RESET_MIC (1 << 15)
#define WDT_RESET_CRT2C (1 << 16)
#define WDT_RESET_PWM (1 << 17)
#define WDT_RESET_PECI (1 << 18)
#define WDT_RESET_JTAG (1 << 19)
#define WDT_RESET_ADC (1 << 20)
#define WDT_RESET_GPIO (1 << 21)
#define WDT_RESET_MCTP (1 << 22)
#define WDT_RESET_XDMA (1 << 23)
#define WDT_RESET_SPI (1 << 24)
#define WDT_RESET_MISC (1 << 25)
watchdog: aspeed: restore default value of reset_mask This is required for the current Linux kernel to reboot. It should also probably be fixed in Linux. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-10-16 11:57:11 +00:00
#define WDT_RESET_DEFAULT \
(WDT_RESET_ARM | WDT_RESET_COPROC | WDT_RESET_I2C | \
WDT_RESET_MAC1 | WDT_RESET_MAC2 | WDT_RESET_GCRT | \
WDT_RESET_USB20 | WDT_RESET_USB11_HOST | WDT_RESET_USB11_EHCI2 | \
WDT_RESET_VIDEO | WDT_RESET_HAC | WDT_RESET_LPC | \
WDT_RESET_SDSDIO | WDT_RESET_MIC | WDT_RESET_CRT2C | \
WDT_RESET_PWM | WDT_RESET_PECI | WDT_RESET_JTAG | \
WDT_RESET_ADC | WDT_RESET_GPIO | WDT_RESET_MISC)
aspeed: Add drivers common to all Aspeed SoCs Add support for Watchdog Timer, which is compatible with AST2400 and AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver does not follow the driver model. It also uses fixed clock, so no clock driver is needed. Add support for timer for Aspeed ast2400/ast2500 devices. The driver actually controls several devices, but because all devices share the same Control Register, it is somewhat difficult to completely decouple them. Since only one timer is needed at the moment, this should be OK. The timer uses fixed clock, so does not rely on a clock driver. Add sysreset driver, which uses watchdog timer to do resets and particular watchdog device to use is hardcoded (0) Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-18 21:44:55 +00:00
#ifndef __ASSEMBLY__
struct ast_wdt {
u32 counter_status;
u32 counter_reload_val;
u32 counter_restart;
u32 ctrl;
u32 timeout_status;
u32 clr_timeout_status;
u32 reset_width;
aspeed: Watchdog Timer Driver This driver supports ast2500 and ast2400 SoCs. Only ast2500 supports reset_mask and thus the option of resettting individual peripherals using WDT. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:22 +00:00
/* On pre-ast2500 SoCs this register is reserved. */
aspeed: Add drivers common to all Aspeed SoCs Add support for Watchdog Timer, which is compatible with AST2400 and AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver does not follow the driver model. It also uses fixed clock, so no clock driver is needed. Add support for timer for Aspeed ast2400/ast2500 devices. The driver actually controls several devices, but because all devices share the same Control Register, it is somewhat difficult to completely decouple them. Since only one timer is needed at the moment, this should be OK. The timer uses fixed clock, so does not rely on a clock driver. Add sysreset driver, which uses watchdog timer to do resets and particular watchdog device to use is hardcoded (0) Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-18 21:44:55 +00:00
u32 reset_mask;
};
aspeed: Watchdog Timer Driver This driver supports ast2500 and ast2400 SoCs. Only ast2500 supports reset_mask and thus the option of resettting individual peripherals using WDT. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:22 +00:00
/**
* Given flags parameter passed to wdt_reset or wdt_start uclass functions,
* gets Reset Mode value from it.
*
* @flags: flags parameter passed into wdt_reset or wdt_start
doc: replace @return by Return: Sphinx expects Return: and not @return to indicate a return value. find . -name '*.c' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; find . -name '*.h' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-01-19 17:05:50 +00:00
* Return: Reset Mode value
aspeed: Watchdog Timer Driver This driver supports ast2500 and ast2400 SoCs. Only ast2500 supports reset_mask and thus the option of resettting individual peripherals using WDT. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:22 +00:00
*/
u32 ast_reset_mode_from_flags(ulong flags);
/**
* Given flags parameter passed to wdt_reset or wdt_start uclass functions,
* gets Reset Mask value from it. Reset Mask is only supported on ast2500
*
* @flags: flags parameter passed into wdt_reset or wdt_start
doc: replace @return by Return: Sphinx expects Return: and not @return to indicate a return value. find . -name '*.c' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; find . -name '*.h' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-01-19 17:05:50 +00:00
* Return: Reset Mask value
aspeed: Watchdog Timer Driver This driver supports ast2500 and ast2400 SoCs. Only ast2500 supports reset_mask and thus the option of resettting individual peripherals using WDT. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:22 +00:00
*/
u32 ast_reset_mask_from_flags(ulong flags);
/**
* Given Reset Mask and Reset Mode values, converts them to flags,
* suitable for passing into wdt_start or wdt_reset uclass functions.
*
* On ast2500 Reset Mask is 25 bits wide and Reset Mode is 2 bits wide, so they
* can both be packed into single 32 bits wide value.
*
* @reset_mode: Reset Mode
* @reset_mask: Reset Mask
*/
ulong ast_flags_from_reset_mode_mask(u32 reset_mode, u32 reset_mask);
aspeed: Add drivers common to all Aspeed SoCs Add support for Watchdog Timer, which is compatible with AST2400 and AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver does not follow the driver model. It also uses fixed clock, so no clock driver is needed. Add support for timer for Aspeed ast2400/ast2500 devices. The driver actually controls several devices, but because all devices share the same Control Register, it is somewhat difficult to completely decouple them. Since only one timer is needed at the moment, this should be OK. The timer uses fixed clock, so does not rely on a clock driver. Add sysreset driver, which uses watchdog timer to do resets and particular watchdog device to use is hardcoded (0) Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-18 21:44:55 +00:00
#endif /* __ASSEMBLY__ */
#endif /* _ASM_ARCH_WDT_H */
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