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u-boot/arch/arm/include/asm/arch-zynq/sys_proto.h

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arm: zynq: Add SLCR support with system reset The patch provides slcr base address initialization support and a support to reset the cpu through slcr driver, hence removed the reset_cpu() from board.c. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-02-04 12:38:59 +01:00
/*
* Copyright (c) 2013 Xilinx Inc.
*
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
2013-07-08 09:37:19 +02:00
* SPDX-License-Identifier: GPL-2.0+
arm: zynq: Add SLCR support with system reset The patch provides slcr base address initialization support and a support to reset the cpu through slcr driver, hence removed the reset_cpu() from board.c. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-02-04 12:38:59 +01:00
*/
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
extern void zynq_slcr_lock(void);
extern void zynq_slcr_unlock(void);
extern void zynq_slcr_cpu_reset(void);
net: zynq_gem: Calculate clock dividers dynamically Remove hard coded clock divider setting and use the Zynq clock framework to dynamically calculate appropriate dividers at run time. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-11-21 13:39:01 -08:00
extern void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate);
fpga: zynq: Add support for loading bitstream Devcfg device requires to load bitstream in binary format. But u-boot also has an option for loading bitstream in bit format. Let's handle both cases by zynqpl driver. Also add suport for loading partial bitstreams. The first driver version was done by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
2013-04-22 15:43:02 +02:00
extern void zynq_slcr_devcfg_disable(void);
extern void zynq_slcr_devcfg_enable(void);
zynq: Add support to find bootmode Added support to find the bootmodes by reading slcr bootmode register. this can be helpful to autoboot the configurations w.r.t a specified bootmode. Added this functionality on board_late_init as it's not needed for normal initializtion part. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-01-09 01:48:21 +05:30
extern u32 zynq_slcr_get_boot_mode(void);
fpga: zynq: Add support for loading bitstream Devcfg device requires to load bitstream in binary format. But u-boot also has an option for loading bitstream in bit format. Let's handle both cases by zynqpl driver. Also add suport for loading partial bitstreams. The first driver version was done by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
2013-04-22 15:43:02 +02:00
extern u32 zynq_slcr_get_idcode(void);
ARM: zynq: Add MIO detection code Add run-time MIO pin detection to get actual pin configuration for specific periphery. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-04-25 12:21:04 +02:00
extern int zynq_slcr_get_mio_pin_status(const char *periph);
zynq: Add new ddrc driver for ECC support The first 1MB is not initialized by first stage bootloader. Check if memory is setup to 16bit mode and ECC is enabled. If it is, clear the first 1MB. Also u-boot should report only the half size of memory. Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-06-17 14:37:01 +02:00
extern void zynq_ddrc_init(void);
ARM: zynq: Added efuse status register base address Added efuse status register base address. This register is used for determining whether efuse was blown or not. Also, added the zynq_get_silicon_version() to get the silicon version of the zynq board. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-11-29 19:01:25 +05:30
extern unsigned int zynq_get_silicon_version(void);
arm: zynq: Add SLCR support with system reset The patch provides slcr base address initialization support and a support to reset the cpu through slcr driver, hence removed the reset_cpu() from board.c. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-02-04 12:38:59 +01:00
mmc: Add support for Xilinx Zynq sdhci controller Add support for SD, MMC and eMMC card on Xilinx Zynq. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
2013-04-22 14:56:49 +02:00
/* Driver extern functions */
mmc: zynq: Use phys_addr_t for addresses phys_addr_t is designed for physical addresses that's why use it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-01-14 16:11:47 +01:00
extern int zynq_sdhci_init(phys_addr_t regbase);
mmc: zynq: Add OF initialization support Enable initialize sdhci from DTB. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-02-24 11:16:31 +01:00
extern int zynq_sdhci_of_init(const void *blob);
mmc: Add support for Xilinx Zynq sdhci controller Add support for SD, MMC and eMMC card on Xilinx Zynq. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
2013-04-22 14:56:49 +02:00
ARM: zynq: Move ps7_init() out of spl.h Prepare for spl.h removal. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-11 14:01:57 +02:00
extern void ps7_init(void);
arm: zynq: Add SLCR support with system reset The patch provides slcr base address initialization support and a support to reset the cpu through slcr driver, hence removed the reset_cpu() from board.c. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-02-04 12:38:59 +01:00
#endif /* _SYS_PROTO_H_ */
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