2019-02-08 15:23:20 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2018 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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#ifndef __G12A_H__
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#define __G12A_H__
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2020-05-10 17:40:13 +00:00
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#ifndef __ASSEMBLY__
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#include <linux/bitops.h>
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#endif
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2019-02-08 15:23:20 +00:00
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#define G12A_AOBUS_BASE 0xff800000
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#define G12A_PERIPHS_BASE 0xff634400
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#define G12A_HIU_BASE 0xff63c000
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#define G12A_ETH_PHY_BASE 0xff64c000
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#define G12A_ETH_BASE 0xff3f0000
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/* Always-On Peripherals registers */
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#define G12A_AO_ADDR(off) (G12A_AOBUS_BASE + ((off) << 2))
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#define G12A_AO_SEC_GP_CFG0 G12A_AO_ADDR(0x90)
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#define G12A_AO_SEC_GP_CFG3 G12A_AO_ADDR(0x93)
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#define G12A_AO_SEC_GP_CFG4 G12A_AO_ADDR(0x94)
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#define G12A_AO_SEC_GP_CFG5 G12A_AO_ADDR(0x95)
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#define G12A_AO_BOOT_DEVICE 0xF
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#define G12A_AO_MEM_SIZE_MASK 0xFFFF0000
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#define G12A_AO_MEM_SIZE_SHIFT 16
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#define G12A_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000
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#define G12A_AO_BL31_RSVMEM_SIZE_SHIFT 16
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#define G12A_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF
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#endif /* __G12A_H__ */
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