2013-04-22 12:56:49 +00:00
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/*
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2015-11-30 15:13:03 +00:00
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* (C) Copyright 2013 - 2015 Xilinx, Inc.
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2013-04-22 12:56:49 +00:00
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*
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* Xilinx Zynq SD Host Controller Interface
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*
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2013-07-08 07:37:19 +00:00
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* SPDX-License-Identifier: GPL-2.0+
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2013-04-22 12:56:49 +00:00
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*/
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#include <common.h>
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2015-11-30 15:13:03 +00:00
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#include <dm.h>
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2014-02-24 10:16:31 +00:00
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#include <fdtdec.h>
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#include <libfdt.h>
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2013-04-22 12:56:49 +00:00
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#include <malloc.h>
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#include <sdhci.h>
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2016-01-05 06:51:04 +00:00
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#ifndef CONFIG_ZYNQ_SDHCI_MIN_FREQ
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# define CONFIG_ZYNQ_SDHCI_MIN_FREQ 0
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#endif
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2016-07-05 23:10:15 +00:00
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struct arasan_sdhci_plat {
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struct mmc_config cfg;
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struct mmc mmc;
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};
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2015-11-30 15:13:03 +00:00
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static int arasan_sdhci_probe(struct udevice *dev)
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2013-04-22 12:56:49 +00:00
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{
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2016-07-05 23:10:15 +00:00
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struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
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2015-11-30 15:13:03 +00:00
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struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
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struct sdhci_host *host = dev_get_priv(dev);
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2016-07-05 23:10:15 +00:00
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u32 caps;
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int ret;
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2013-04-22 12:56:49 +00:00
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2014-07-08 10:01:04 +00:00
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host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
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2014-01-22 08:17:09 +00:00
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SDHCI_QUIRK_BROKEN_R1B;
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2016-01-12 09:42:16 +00:00
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#ifdef CONFIG_ZYNQ_HISPD_BROKEN
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host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
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#endif
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2013-04-22 12:56:49 +00:00
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host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
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2016-07-05 23:10:15 +00:00
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caps = sdhci_readl(host, SDHCI_CAPABILITIES);
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ret = sdhci_setup_cfg(&plat->cfg, dev->name, host->bus_width,
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caps, CONFIG_ZYNQ_SDHCI_MAX_FREQ,
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CONFIG_ZYNQ_SDHCI_MIN_FREQ, host->version,
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host->quirks, 0);
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host->mmc = &plat->mmc;
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if (ret)
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return ret;
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host->mmc->priv = host;
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2016-05-01 19:52:34 +00:00
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host->mmc->dev = dev;
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2016-07-05 23:10:15 +00:00
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upriv->mmc = host->mmc;
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2015-11-30 15:13:03 +00:00
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2016-07-05 23:10:15 +00:00
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return sdhci_probe(dev);
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2013-04-22 12:56:49 +00:00
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}
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2015-11-30 15:13:03 +00:00
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static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
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{
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struct sdhci_host *host = dev_get_priv(dev);
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2016-04-22 11:59:31 +00:00
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host->name = dev->name;
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2015-11-30 15:13:03 +00:00
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host->ioaddr = (void *)dev_get_addr(dev);
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return 0;
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}
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2016-07-05 23:10:15 +00:00
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static int arasan_sdhci_bind(struct udevice *dev)
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{
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struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
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int ret;
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ret = sdhci_bind(dev, &plat->mmc, &plat->cfg);
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if (ret)
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return ret;
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return 0;
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}
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2015-11-30 15:13:03 +00:00
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static const struct udevice_id arasan_sdhci_ids[] = {
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{ .compatible = "arasan,sdhci-8.9a" },
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{ }
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};
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U_BOOT_DRIVER(arasan_sdhci_drv) = {
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.name = "arasan_sdhci",
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.id = UCLASS_MMC,
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.of_match = arasan_sdhci_ids,
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.ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
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2016-07-05 23:10:15 +00:00
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.ops = &sdhci_ops,
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.bind = arasan_sdhci_bind,
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2015-11-30 15:13:03 +00:00
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.probe = arasan_sdhci_probe,
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.priv_auto_alloc_size = sizeof(struct sdhci_host),
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2016-07-05 23:10:15 +00:00
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.platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat),
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2015-11-30 15:13:03 +00:00
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};
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