2015-08-13 02:55:34 +00:00
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/*
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* (C) Copyright 2009
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* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SYS_PROTO_H_
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#define _SYS_PROTO_H_
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#include <asm/imx-common/regs-common.h>
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#include <common.h>
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#include "../arch-imx/cpu.h"
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#define soc_rev() (get_cpu_rev() & 0xFF)
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#define is_soc_rev(rev) (soc_rev() == rev)
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/* returns MXC_CPU_ value */
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#define cpu_type(rev) (((rev) >> 12) & 0xff)
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2015-09-02 18:54:12 +00:00
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#define soc_type(rev) (((rev) >> 12) & 0xf0)
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2015-08-13 02:55:34 +00:00
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/* both macros return/take MXC_CPU_ constants */
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#define get_cpu_type() (cpu_type(get_cpu_rev()))
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2015-09-02 18:54:12 +00:00
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#define get_soc_type() (soc_type(get_cpu_rev()))
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2015-08-13 02:55:34 +00:00
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#define is_cpu_type(cpu) (get_cpu_type() == cpu)
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2015-09-02 18:54:12 +00:00
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#define is_soc_type(soc) (get_soc_type() == soc)
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2015-08-13 02:55:34 +00:00
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2016-05-23 10:35:52 +00:00
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#define is_mx6() (is_soc_type(MXC_SOC_MX6))
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#define is_mx7() (is_soc_type(MXC_SOC_MX7))
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2015-08-13 02:55:34 +00:00
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#define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
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2016-05-23 10:35:52 +00:00
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#define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
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#define is_mx6sdl() (is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6DL))
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#define is_mx6sx() (is_cpu_type(MXC_CPU_MX6SX))
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#define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL))
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#define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL))
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2015-08-13 02:55:34 +00:00
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u32 get_nr_cpus(void);
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u32 get_cpu_rev(void);
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u32 get_cpu_speed_grade_hz(void);
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u32 get_cpu_temp_grade(int *minc, int *maxc);
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const char *get_imx_type(u32 imxtype);
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u32 imx_ddr_size(void);
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void sdelay(unsigned long);
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void set_chipselect_size(int const);
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2015-09-02 18:54:15 +00:00
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void init_aips(void);
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void init_src(void);
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2015-09-02 18:54:21 +00:00
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void imx_set_wdog_powerdown(bool enable);
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2015-09-02 18:54:15 +00:00
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2015-08-13 02:55:34 +00:00
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/*
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* Initializes on-chip ethernet controllers.
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* to override, implement board_eth_init()
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*/
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int fecmxc_initialize(bd_t *bis);
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u32 get_ahb_clk(void);
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u32 get_periph_clk(void);
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2015-10-29 07:54:49 +00:00
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void lcdif_power_down(void);
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2015-08-13 02:55:34 +00:00
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int mxs_reset_block(struct mxs_register_32 *reg);
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int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout);
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int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
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#endif
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