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u-boot/arch/powerpc/cpu/mpc85xx/p4080_serdes.c

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SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
// SPDX-License-Identifier: GPL-2.0+
powerpc/p4080: Add support for initializing SERDES Add support for initializing the SERDES blocks on CoreNet style QoriQ devices and the p4080 specific SERDES tables to know which actual componetns are enabled. Additionally, split out the Frame Manger (FMAN) into its specific ethernet ports instead of gross level of the full FMAN. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-13 03:51:29 +00:00
/*
* Copyright 2009-2010 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <asm/io.h>
#include <asm/fsl_serdes.h>
#include <asm/processor.h>
#include <asm/io.h>
#include "fsl_corenet_serdes.h"
static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
[0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
[0x5] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
[0x8] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
[0xd] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SGMII_FM2_DTSEC3,
SGMII_FM2_DTSEC4, AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2,
XAUI_FM2, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
[0xe] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, SGMII_FM2_DTSEC3,
SGMII_FM2_DTSEC4, AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2,
XAUI_FM2, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
[0xf] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, AURORA, AURORA, XAUI_FM2,
XAUI_FM2, XAUI_FM2, XAUI_FM2, NONE, NONE, NONE, NONE},
[0x10] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM2_DTSEC1,
SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
NONE, NONE, NONE, NONE},
[0x13] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
[0x16] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
AURORA, AURORA, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC1,
SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4},
[0x19] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, SGMII_FM1_DTSEC1,
SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4},
[0x1d] = {PCIE1, PCIE1, PCIE3, PCIE3, NONE, SRIO2, NONE, SRIO1,
AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
[0x22] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
[0x25] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1,
AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
};
powerpc/p4080: Add workaround for errata SERDES8 Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-13 05:39:46 +00:00
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
uint16_t srds_lpd_b[SRDS_MAX_BANK];
#endif
powerpc/p4080: Add support for initializing SERDES Add support for initializing the SERDES blocks on CoreNet style QoriQ devices and the p4080 specific SERDES tables to know which actual componetns are enabled. Additionally, split out the Frame Manger (FMAN) into its specific ethernet ports instead of gross level of the full FMAN. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-13 03:51:29 +00:00
enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
{
if (!serdes_lane_enabled(lane))
return NONE;
return serdes_cfg_tbl[cfg][lane];
}
int is_serdes_prtcl_valid(u32 prtcl) {
int i;
powerpc: mpc85xx/mpc86xx: Fix off-by-one boundary checking with ARRAY_SIZE If a variable is used as array subscript, it's valid value range is 0 ... ARRAY_SIZE -1. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-26 07:00:30 +00:00
if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
powerpc/p4080: Add support for initializing SERDES Add support for initializing the SERDES blocks on CoreNet style QoriQ devices and the p4080 specific SERDES tables to know which actual componetns are enabled. Additionally, split out the Frame Manger (FMAN) into its specific ethernet ports instead of gross level of the full FMAN. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-13 03:51:29 +00:00
return 0;
for (i = 0; i < SRDS_MAX_LANES; i++) {
if (serdes_cfg_tbl[prtcl][i] != NONE)
return 1;
}
return 0;
}
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