mirror of
https://github.com/AsahiLinux/u-boot
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173 lines
4.2 KiB
C
173 lines
4.2 KiB
C
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/*
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* S3C24x0 LCD driver
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*
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* NOTE: Only 16/24 bpp operation with TFT LCD is supported.
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*
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* Copyright (C) 2014 Marek Vasut <marex@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <malloc.h>
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#include <video_fb.h>
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#include <asm/errno.h>
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#include <asm/io.h>
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#include <asm/arch/s3c24x0_cpu.h>
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#include "videomodes.h"
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static GraphicDevice panel;
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/* S3C requires the FB to be 4MiB aligned. */
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#define S3CFB_ALIGN (4 << 20)
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#define S3CFB_LCDCON1_CLKVAL(x) ((x) << 8)
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#define S3CFB_LCDCON1_PNRMODE_TFT (0x3 << 5)
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#define S3CFB_LCDCON1_BPPMODE_TFT_16BPP (0xc << 1)
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#define S3CFB_LCDCON1_BPPMODE_TFT_24BPP (0xd << 1)
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#define S3CFB_LCDCON2_VBPD(x) ((x) << 24)
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#define S3CFB_LCDCON2_LINEVAL(x) ((x) << 14)
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#define S3CFB_LCDCON2_VFPD(x) ((x) << 6)
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#define S3CFB_LCDCON2_VSPW(x) ((x) << 0)
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#define S3CFB_LCDCON3_HBPD(x) ((x) << 19)
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#define S3CFB_LCDCON3_HOZVAL(x) ((x) << 8)
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#define S3CFB_LCDCON3_HFPD(x) ((x) << 0)
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#define S3CFB_LCDCON4_HSPW(x) ((x) << 0)
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#define S3CFB_LCDCON5_BPP24BL (1 << 12)
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#define S3CFB_LCDCON5_FRM565 (1 << 11)
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#define S3CFB_LCDCON5_HWSWP (1 << 0)
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#define PS2KHZ(ps) (1000000000UL / (ps))
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/*
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* Example:
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* setenv videomode video=ctfb:x:800,y:480,depth:16,mode:0,\
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* pclk:30066,le:41,ri:89,up:45,lo:12,
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* hs:1,vs:1,sync:100663296,vmode:0
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*/
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static void s3c_lcd_init(GraphicDevice *panel,
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struct ctfb_res_modes *mode, int bpp)
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{
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uint32_t clk_divider;
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struct s3c24x0_lcd *regs = s3c24x0_get_base_lcd();
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/* Stop the controller. */
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clrbits_le32(®s->lcdcon1, 1);
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/* Calculate clock divider. */
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clk_divider = (get_HCLK() / PS2KHZ(mode->pixclock)) / 1000;
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clk_divider = DIV_ROUND_UP(clk_divider, 2);
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if (clk_divider)
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clk_divider -= 1;
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/* Program LCD configuration. */
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switch (bpp) {
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case 16:
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writel(S3CFB_LCDCON1_BPPMODE_TFT_16BPP |
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S3CFB_LCDCON1_PNRMODE_TFT |
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S3CFB_LCDCON1_CLKVAL(clk_divider),
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®s->lcdcon1);
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writel(S3CFB_LCDCON5_HWSWP | S3CFB_LCDCON5_FRM565,
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®s->lcdcon5);
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break;
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case 24:
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writel(S3CFB_LCDCON1_BPPMODE_TFT_24BPP |
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S3CFB_LCDCON1_PNRMODE_TFT |
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S3CFB_LCDCON1_CLKVAL(clk_divider),
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®s->lcdcon1);
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writel(S3CFB_LCDCON5_BPP24BL, ®s->lcdcon5);
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break;
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}
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writel(S3CFB_LCDCON2_LINEVAL(mode->yres - 1) |
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S3CFB_LCDCON2_VBPD(mode->upper_margin - 1) |
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S3CFB_LCDCON2_VFPD(mode->lower_margin - 1) |
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S3CFB_LCDCON2_VSPW(mode->vsync_len - 1),
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®s->lcdcon2);
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writel(S3CFB_LCDCON3_HBPD(mode->right_margin - 1) |
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S3CFB_LCDCON3_HFPD(mode->left_margin - 1) |
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S3CFB_LCDCON3_HOZVAL(mode->xres - 1),
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®s->lcdcon3);
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writel(S3CFB_LCDCON4_HSPW(mode->hsync_len - 1),
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®s->lcdcon4);
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/* Write FB address. */
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writel(panel->frameAdrs >> 1, ®s->lcdsaddr1);
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writel((panel->frameAdrs +
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(mode->xres * mode->yres * panel->gdfBytesPP)) >> 1,
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®s->lcdsaddr2);
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writel(mode->xres * bpp / 16, ®s->lcdsaddr3);
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/* Start the controller. */
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setbits_le32(®s->lcdcon1, 1);
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}
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void *video_hw_init(void)
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{
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int bpp = -1;
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char *penv;
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void *fb;
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struct ctfb_res_modes mode;
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puts("Video: ");
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/* Suck display configuration from "videomode" variable */
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penv = getenv("videomode");
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if (!penv) {
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puts("S3CFB: 'videomode' variable not set!\n");
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return NULL;
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}
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bpp = video_get_params(&mode, penv);
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/* fill in Graphic device struct */
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sprintf(panel.modeIdent, "%dx%dx%d", mode.xres, mode.yres, bpp);
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panel.winSizeX = mode.xres;
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panel.winSizeY = mode.yres;
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panel.plnSizeX = mode.xres;
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panel.plnSizeY = mode.yres;
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switch (bpp) {
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case 24:
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panel.gdfBytesPP = 4;
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panel.gdfIndex = GDF_32BIT_X888RGB;
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break;
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case 16:
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panel.gdfBytesPP = 2;
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panel.gdfIndex = GDF_16BIT_565RGB;
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break;
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default:
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printf("S3CFB: Invalid BPP specified! (bpp = %i)\n", bpp);
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return NULL;
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}
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panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP;
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/* Allocate framebuffer */
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fb = memalign(S3CFB_ALIGN, roundup(panel.memSize, S3CFB_ALIGN));
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if (!fb) {
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printf("S3CFB: Error allocating framebuffer!\n");
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return NULL;
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}
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/* Wipe framebuffer */
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memset(fb, 0, panel.memSize);
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panel.frameAdrs = (u32)fb;
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printf("%s\n", panel.modeIdent);
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/* Start framebuffer */
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s3c_lcd_init(&panel, &mode, bpp);
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return (void *)&panel;
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}
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