2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2013-11-21 08:06:46 +00:00
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/*
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* include/configs/lager.h
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* This file is lager board configuration.
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*
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2014-11-10 05:34:07 +00:00
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* Copyright (C) 2013, 2014 Renesas Electronics Corporation
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2013-11-21 08:06:46 +00:00
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*/
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#ifndef __LAGER_H
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#define __LAGER_H
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2014-11-10 05:34:07 +00:00
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#include "rcar-gen2-common.h"
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2014-03-31 06:22:31 +00:00
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2018-04-23 18:24:06 +00:00
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#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000
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#define STACK_AREA_SIZE 0x00100000
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#define LOW_LEVEL_MERAM_STACK \
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2013-11-21 08:06:46 +00:00
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(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
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/* MEMORY */
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2014-11-10 05:34:07 +00:00
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#define RCAR_GEN2_SDRAM_BASE 0x40000000
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#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024)
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#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
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2013-11-21 08:06:46 +00:00
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2013-10-20 11:28:24 +00:00
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/* SH Ether */
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#define CONFIG_SH_ETHER_USE_PORT 0
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#define CONFIG_SH_ETHER_PHY_ADDR 0x1
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#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
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#define CONFIG_SH_ETHER_CACHE_WRITEBACK
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#define CONFIG_SH_ETHER_CACHE_INVALIDATE
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2018-04-23 18:24:06 +00:00
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#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
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2013-10-20 11:28:24 +00:00
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#define CONFIG_BITBANGMII_MULTI
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2013-11-21 08:06:46 +00:00
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/* Board Clock */
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2014-03-31 05:03:07 +00:00
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#define RMOBILE_XTAL_CLK 20000000u
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#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
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2013-11-21 08:06:46 +00:00
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2018-04-23 18:24:06 +00:00
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#define CONFIG_EXTRA_ENV_SETTINGS \
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2018-11-26 23:19:03 +00:00
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"bootm_size=0x10000000\0"
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2018-04-23 18:24:06 +00:00
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/* SPL support */
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#define CONFIG_SPL_STACK 0xe6340000
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#define CONFIG_SPL_MAX_SIZE 0x4000
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_CONS_SCIF0
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#define CONFIG_SH_SCIF_CLK_FREQ 65000000
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#endif
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2014-11-21 01:19:32 +00:00
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2013-11-21 08:06:46 +00:00
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#endif /* __LAGER_H */
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