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u-boot/drivers/spi/cadence_qspi.h

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SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
/* SPDX-License-Identifier: GPL-2.0+ */
spi: Add Cadence QSPI DM driver used by SoCFPGA This driver is cloned from the Altera Rockerboard.org U-Boot repository. I used this git tag: ACDS14.0.1_REL_GSRD_RC2. With Some modification to support the U-Boot driver model (DM). As mentioned above, in this new version I ported this driver to the new driver model (DM). One big advantage of this move is that now multiple SPI drivers can be enabled on one platform. And since the SoCFPGA also has the Designware SPI master controller integrated, this feature is really needed to support both controllers. Because of this, this series needs the DT support for SoCFPGA to be applied. For DT based probing in the SPI DM. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-11-07 11:37:49 +00:00
/*
* Copyright (C) 2012
* Altera Corporation <www.altera.com>
*/
#ifndef __CADENCE_QSPI_H__
#define __CADENCE_QSPI_H__
#define CQSPI_IS_ADDR(cmd_len) (cmd_len > 1 ? 1 : 0)
#define CQSPI_NO_DECODER_MAX_CS 4
#define CQSPI_DECODER_MAX_CS 16
#define CQSPI_READ_CAPTURE_MAX_DELAY 16
struct cadence_spi_platdata {
unsigned int max_hz;
void *regbase;
void *ahbbase;
spi: cadence_spi: Sync DT bindings with Linux Adopt the Linux DT bindings. This also fixes an issue with the indaddrtrig register on the Cadence QSPI device being programmed with the wrong value for the socfpga arch. Tested on TI K2G platform: Tested-by: Vignesh R <vigneshr@ti.com> Tested on a socfpga-cyclonev board: Tested-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Signed-off-by: Jason Rush <jarush@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Acked-by: Marek Vasut <marex@denx.de>
2018-01-23 23:13:09 +00:00
bool is_decoded_cs;
u32 fifo_depth;
u32 fifo_width;
u32 trigger_address;
spi: Add Cadence QSPI DM driver used by SoCFPGA This driver is cloned from the Altera Rockerboard.org U-Boot repository. I used this git tag: ACDS14.0.1_REL_GSRD_RC2. With Some modification to support the U-Boot driver model (DM). As mentioned above, in this new version I ported this driver to the new driver model (DM). One big advantage of this move is that now multiple SPI drivers can be enabled on one platform. And since the SoCFPGA also has the Designware SPI master controller integrated, this feature is really needed to support both controllers. Because of this, this series needs the DT support for SoCFPGA to be applied. For DT based probing in the SPI DM. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-11-07 11:37:49 +00:00
spi: cadence_spi: Sync DT bindings with Linux Adopt the Linux DT bindings. This also fixes an issue with the indaddrtrig register on the Cadence QSPI device being programmed with the wrong value for the socfpga arch. Tested on TI K2G platform: Tested-by: Vignesh R <vigneshr@ti.com> Tested on a socfpga-cyclonev board: Tested-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Signed-off-by: Jason Rush <jarush@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Acked-by: Marek Vasut <marex@denx.de>
2018-01-23 23:13:09 +00:00
/* Flash parameters */
spi: Add Cadence QSPI DM driver used by SoCFPGA This driver is cloned from the Altera Rockerboard.org U-Boot repository. I used this git tag: ACDS14.0.1_REL_GSRD_RC2. With Some modification to support the U-Boot driver model (DM). As mentioned above, in this new version I ported this driver to the new driver model (DM). One big advantage of this move is that now multiple SPI drivers can be enabled on one platform. And since the SoCFPGA also has the Designware SPI master controller integrated, this feature is really needed to support both controllers. Because of this, this series needs the DT support for SoCFPGA to be applied. For DT based probing in the SPI DM. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-11-07 11:37:49 +00:00
u32 page_size;
u32 block_size;
u32 tshsl_ns;
u32 tsd2d_ns;
u32 tchsh_ns;
u32 tslch_ns;
};
struct cadence_spi_priv {
void *regbase;
void *ahbbase;
size_t cmd_len;
u8 cmd_buf[32];
size_t data_len;
int qspi_is_init;
unsigned int qspi_calibrated_hz;
unsigned int qspi_calibrated_cs;
spi: cadence_qspi: Ensure spi_calibration is run when sclk change Ensuring spi_calibration is run when there is a change of sclk frequency. This will ensure the qspi flash access works for high sclk frequency Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vikas Manocha <vikas.manocha@st.com> Cc: Jagannadh Teki <jteki@openedev.com> Cc: Pavel Machek <pavel@denx.de> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-10-17 13:31:55 +00:00
unsigned int previous_hz;
spi: Add Cadence QSPI DM driver used by SoCFPGA This driver is cloned from the Altera Rockerboard.org U-Boot repository. I used this git tag: ACDS14.0.1_REL_GSRD_RC2. With Some modification to support the U-Boot driver model (DM). As mentioned above, in this new version I ported this driver to the new driver model (DM). One big advantage of this move is that now multiple SPI drivers can be enabled on one platform. And since the SoCFPGA also has the Designware SPI master controller integrated, this feature is really needed to support both controllers. Because of this, this series needs the DT support for SoCFPGA to be applied. For DT based probing in the SPI DM. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-11-07 11:37:49 +00:00
};
/* Functions call declaration */
void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat);
void cadence_qspi_apb_controller_enable(void *reg_base_addr);
void cadence_qspi_apb_controller_disable(void *reg_base_addr);
int cadence_qspi_apb_command_read(void *reg_base_addr,
unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen, u8 *rxbuf);
int cadence_qspi_apb_command_write(void *reg_base_addr,
unsigned int cmdlen, const u8 *cmdbuf,
unsigned int txlen, const u8 *txbuf);
int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
spi: cadence_quadspi: Enable QUAD mode based on DT data Instead of relying on CONFIG_SPI_FLASH_QUAD to be defined to enable QUAD mode, make use of mode_rx field of dm_spi_slave_platdata to determine whether to enable or disable QUAD mode. This is necessary to support muliple SPI controllers where one of them may not support QUAD mode. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com>
2016-07-06 04:50:56 +00:00
unsigned int cmdlen, unsigned int rx_width, const u8 *cmdbuf);
spi: Add Cadence QSPI DM driver used by SoCFPGA This driver is cloned from the Altera Rockerboard.org U-Boot repository. I used this git tag: ACDS14.0.1_REL_GSRD_RC2. With Some modification to support the U-Boot driver model (DM). As mentioned above, in this new version I ported this driver to the new driver model (DM). One big advantage of this move is that now multiple SPI drivers can be enabled on one platform. And since the SoCFPGA also has the Designware SPI master controller integrated, this feature is really needed to support both controllers. Because of this, this series needs the DT support for SoCFPGA to be applied. For DT based probing in the SPI DM. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-11-07 11:37:49 +00:00
int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
unsigned int rxlen, u8 *rxbuf);
int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
unsigned int cmdlen, const u8 *cmdbuf);
int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
unsigned int txlen, const u8 *txbuf);
void cadence_qspi_apb_chipselect(void *reg_base,
unsigned int chip_select, unsigned int decoder_enable);
spi: cadence_qspi: Use spi mode at the point it is needed Instead of extracting mode settings and passing them as separate args to another function, just pass the SPI mode as an arg. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2016-11-29 12:58:31 +00:00
void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode);
spi: Add Cadence QSPI DM driver used by SoCFPGA This driver is cloned from the Altera Rockerboard.org U-Boot repository. I used this git tag: ACDS14.0.1_REL_GSRD_RC2. With Some modification to support the U-Boot driver model (DM). As mentioned above, in this new version I ported this driver to the new driver model (DM). One big advantage of this move is that now multiple SPI drivers can be enabled on one platform. And since the SoCFPGA also has the Designware SPI master controller integrated, this feature is really needed to support both controllers. Because of this, this series needs the DT support for SoCFPGA to be applied. For DT based probing in the SPI DM. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-11-07 11:37:49 +00:00
void cadence_qspi_apb_config_baudrate_div(void *reg_base,
unsigned int ref_clk_hz, unsigned int sclk_hz);
void cadence_qspi_apb_delay(void *reg_base,
unsigned int ref_clk, unsigned int sclk_hz,
unsigned int tshsl_ns, unsigned int tsd2d_ns,
unsigned int tchsh_ns, unsigned int tslch_ns);
void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy);
void cadence_qspi_apb_readdata_capture(void *reg_base,
unsigned int bypass, unsigned int delay);
#endif /* __CADENCE_QSPI_H__ */
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