2018-05-06 21:58:06 +00:00
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# SPDX-License-Identifier: GPL-2.0+
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2013-12-14 03:47:35 +00:00
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#
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# (C) Copyright 2000-2003
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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extra-y := start.o
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obj-y += cpu.o
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2017-07-28 15:38:42 +00:00
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ifndef CONFIG_$(SPL_TPL_)TIMER
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2018-04-12 01:24:46 +00:00
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obj-$(CONFIG_SYS_ARCH_TIMER) += generic_timer.o
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2017-07-28 15:38:42 +00:00
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endif
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2020-12-28 12:13:13 +00:00
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ifndef CONFIG_$(SPL_)SYS_DCACHE_OFF
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2013-12-14 03:47:35 +00:00
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obj-y += cache_v8.o
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2020-12-28 12:13:13 +00:00
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obj-y += cache.o
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endif
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armv8: make SPL exception vectors optional
Even though the exception vector table is a fundamental part of the ARM
architecture, U-Boot mostly does not make real use of it, except when
crash dumping. But having it in takes up quite some space, partly due to
the architectural alignment requirement of 2KB. Since we don't take special
care of that, the compiler adds a more or less random amount of padding
space, which increases the image size quite a bit, especially for the SPL.
On a typical Allwinner build this is around 1.5KB of padding, plus 1KB
for the vector table (mostly padding space again), then some extra code
to do the actual handling. This amounts to almost 10% of the maximum image
size, which is quite a lot for a pure debugging feature.
Add a Kconfig symbol to allow the exception vector table to be left out
of the build for the SPL.
For now this is "default y" for everyone, but specific defconfigs,
platforms or .config files can opt out here at will, to mitigate the code
size pressure we see for some SPLs.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-07-24 23:57:01 +00:00
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ifdef CONFIG_SPL_BUILD
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obj-$(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) += exceptions.o
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else
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2013-12-14 03:47:35 +00:00
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obj-y += exceptions.o
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2019-01-08 17:13:06 +00:00
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obj-y += exception_level.o
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armv8: make SPL exception vectors optional
Even though the exception vector table is a fundamental part of the ARM
architecture, U-Boot mostly does not make real use of it, except when
crash dumping. But having it in takes up quite some space, partly due to
the architectural alignment requirement of 2KB. Since we don't take special
care of that, the compiler adds a more or less random amount of padding
space, which increases the image size quite a bit, especially for the SPL.
On a typical Allwinner build this is around 1.5KB of padding, plus 1KB
for the vector table (mostly padding space again), then some extra code
to do the actual handling. This amounts to almost 10% of the maximum image
size, which is quite a lot for a pure debugging feature.
Add a Kconfig symbol to allow the exception vector table to be left out
of the build for the SPL.
For now this is "default y" for everyone, but specific defconfigs,
platforms or .config files can opt out here at will, to mitigate the code
size pressure we see for some SPLs.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-07-24 23:57:01 +00:00
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endif
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2013-12-14 03:47:35 +00:00
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obj-y += tlb.o
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obj-y += transition.o
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2019-02-12 08:27:03 +00:00
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ifndef CONFIG_ARMV8_PSCI
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2015-10-14 16:55:46 +00:00
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obj-y += fwcall.o
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2019-02-12 08:27:03 +00:00
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endif
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2016-06-28 12:18:16 +00:00
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obj-y += cpu-dt.o
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2017-04-14 02:10:23 +00:00
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obj-$(CONFIG_ARM_SMCCC) += smccc-call.o
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2016-06-27 10:31:05 +00:00
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ifndef CONFIG_SPL_BUILD
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obj-$(CONFIG_ARMV8_SPIN_TABLE) += spin_table.o spin_table_v8.o
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sunxi: Add arm64 FEL support
So far we did not support the BootROM based FEL USB debug mode on the
64-bit builds for Allwinner SoCs: The BootROM is using AArch32, but the
SPL runs in AArch64.
Returning back to AArch32 was not working as expected, since the RMR
reset into 32-bit mode always starts execution in the BootROM, but not
in the FEL routine.
After some debug and research and with help via IRC, the CPU hotplug
mechanism emerged as a solution: If a certain R_CPUCFG register contains
some magic, the BootROM will immediately branch to an address stored in
some other register. This works well for our purposes.
Enable the FEL feature by providing early AArch32 code to first save the
FEL state, *before* initially entering AArch64.
If we eventually determine that we should return to FEL, we reset back
into AArch32, and use the CPU hotplug mechanism to run some small
AArch32 code snippet that restores the initially saved FEL state.
That allows the normal AArch64 SPL build to be loaded via the sunxi-fel
tool, with it returning into FEL mode, so that other payloads can be
transferred via FEL as well.
Tested on A64, H5 and H6.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Priit Laes <plaes@plaes.org> (on Olimex A64-Olinuxino)
2016-08-23 21:19:30 +00:00
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else
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obj-$(CONFIG_ARCH_SUNXI) += fel_utils.o
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2016-06-27 10:31:05 +00:00
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endif
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2017-01-16 09:31:47 +00:00
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obj-$(CONFIG_$(SPL_)ARMV8_SEC_FIRMWARE_SUPPORT) += sec_firmware.o sec_firmware_asm.o
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2014-11-13 03:28:40 +00:00
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2020-05-05 12:28:41 +00:00
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ifdef CONFIG_SPL_BUILD
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obj-$(CONFIG_SPL_RECOVER_DATA_SECTION) += spl_data.o
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endif
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2015-10-26 11:47:50 +00:00
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obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/
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2016-06-05 00:43:00 +00:00
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obj-$(CONFIG_S32V234) += s32v234/
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2015-07-30 17:55:20 +00:00
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obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
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2016-12-08 03:58:24 +00:00
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obj-$(CONFIG_ARMV8_PSCI) += psci.o
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2020-07-15 17:18:56 +00:00
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obj-$(CONFIG_TARGET_BCMNS3) += bcmns3/
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2020-08-06 09:42:47 +00:00
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obj-$(CONFIG_XEN) += xen/
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2022-06-01 18:26:29 +00:00
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obj-$(CONFIG_ARMV8_CE_SHA1) += sha1_ce_glue.o sha1_ce_core.o
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2022-06-01 18:26:31 +00:00
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obj-$(CONFIG_ARMV8_CE_SHA256) += sha256_ce_glue.o sha256_ce_core.o
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