2013-04-01 22:48:54 +00:00
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/*
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* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
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*
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2016-01-15 03:05:13 +00:00
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* SPDX-License-Identifier: GPL-2.0
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2013-04-01 22:48:54 +00:00
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*/
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#ifndef _TEGRA114_SYSCTR_H_
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#define _TEGRA114_SYSCTR_H_
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struct sysctr_ctlr {
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u32 cntcr; /* 0x00: SYSCTR0_CNTCR Counter Control */
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u32 cntsr; /* 0x04: SYSCTR0_CNTSR Counter Status */
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u32 cntcv0; /* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */
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u32 cntcv1; /* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */
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u32 reserved1[4]; /* 0x10 - 0x1C */
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u32 cntfid0; /* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */
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u32 cntfid1; /* 0x24: SYSCTR0_CNTFID1 Freq Table End */
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u32 reserved2[1002]; /* 0x28 - 0xFCC */
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u32 counterid[12]; /* 0xFD0 - 0xFxx CounterID regs, RO */
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};
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#define TSC_CNTCR_ENABLE (1 << 0) /* Enable */
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#define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */
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#endif /* _TEGRA114_SYSCTR_H_ */
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