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u-boot/arch/arm/dts/ast2500.dtsi

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aspeed: Add basic ast2500-specific drivers and configuration Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-18 21:44:56 +00:00
/*
* This device tree is copied from
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
* https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi
aspeed: Add basic ast2500-specific drivers and configuration Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-18 21:44:56 +00:00
*/
#include "skeleton.dtsi"
/ {
model = "Aspeed BMC";
compatible = "aspeed,ast2500";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&vic>;
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &i2c7;
i2c8 = &i2c8;
i2c9 = &i2c9;
i2c10 = &i2c10;
i2c11 = &i2c11;
i2c12 = &i2c12;
i2c13 = &i2c13;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
serial4 = &uart5;
serial5 = &vuart;
};
aspeed: Add basic ast2500-specific drivers and configuration Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-18 21:44:56 +00:00
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,arm1176jzf-s";
device_type = "cpu";
reg = <0>;
};
};
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0>;
};
aspeed: Add basic ast2500-specific drivers and configuration Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-18 21:44:56 +00:00
ahb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
fmc: flash-controller@1e620000 {
arm: dts: aspeed: Update SPI flash node settings For both AST2500 and AST2600, there are three SPI controllers, FMC(Firmware Memory Controller), SPI1 and SPI2. The clock source is HCLK. Following is the basic information for ASPEED SPI controller. AST2500: - FMC: CS number: 3 controller reg: 0x1e620000 - 0x1e62ffff decoded address: 0x20000000 - 0x2fffffff - SPI1: CS number: 2 controller reg: 0x1e630000 - 0x1e630fff decoded address: 0x30000000 - 0x37ffffff - SPI2: CS number: 2 controller reg: 0x1e631000 - 0x1e631fff decoded address: 0x38000000 - 0x3fffffff AST2600: - FMC: CS number: 3 controller reg: 0x1e620000 - 0x1e62ffff decoded address: 0x20000000 - 0x2fffffff - SPI1: CS number: 2 controller reg: 0x1e630000 - 0x1e630fff decoded address: 0x30000000 - 0x3fffffff - SPI2: CS number: 3 controller reg: 0x1e631000 - 0x1e631fff decoded address: 0x50000000 - 0x5fffffff Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
2022-08-19 09:01:07 +00:00
reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-fmc";
arm: dts: aspeed: Update SPI flash node settings For both AST2500 and AST2600, there are three SPI controllers, FMC(Firmware Memory Controller), SPI1 and SPI2. The clock source is HCLK. Following is the basic information for ASPEED SPI controller. AST2500: - FMC: CS number: 3 controller reg: 0x1e620000 - 0x1e62ffff decoded address: 0x20000000 - 0x2fffffff - SPI1: CS number: 2 controller reg: 0x1e630000 - 0x1e630fff decoded address: 0x30000000 - 0x37ffffff - SPI2: CS number: 2 controller reg: 0x1e631000 - 0x1e631fff decoded address: 0x38000000 - 0x3fffffff AST2600: - FMC: CS number: 3 controller reg: 0x1e620000 - 0x1e62ffff decoded address: 0x20000000 - 0x2fffffff - SPI1: CS number: 2 controller reg: 0x1e630000 - 0x1e630fff decoded address: 0x30000000 - 0x3fffffff - SPI2: CS number: 3 controller reg: 0x1e631000 - 0x1e631fff decoded address: 0x50000000 - 0x5fffffff Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
2022-08-19 09:01:07 +00:00
clocks = <&scu ASPEED_CLK_AHB>;
num-cs = <3>;
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
status = "disabled";
arm: dts: aspeed: Update SPI flash node settings For both AST2500 and AST2600, there are three SPI controllers, FMC(Firmware Memory Controller), SPI1 and SPI2. The clock source is HCLK. Following is the basic information for ASPEED SPI controller. AST2500: - FMC: CS number: 3 controller reg: 0x1e620000 - 0x1e62ffff decoded address: 0x20000000 - 0x2fffffff - SPI1: CS number: 2 controller reg: 0x1e630000 - 0x1e630fff decoded address: 0x30000000 - 0x37ffffff - SPI2: CS number: 2 controller reg: 0x1e631000 - 0x1e631fff decoded address: 0x38000000 - 0x3fffffff AST2600: - FMC: CS number: 3 controller reg: 0x1e620000 - 0x1e62ffff decoded address: 0x20000000 - 0x2fffffff - SPI1: CS number: 2 controller reg: 0x1e630000 - 0x1e630fff decoded address: 0x30000000 - 0x3fffffff - SPI2: CS number: 3 controller reg: 0x1e631000 - 0x1e631fff decoded address: 0x50000000 - 0x5fffffff Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
2022-08-19 09:01:07 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
status = "disabled";
};
arm: dts: aspeed: Update SPI flash node settings For both AST2500 and AST2600, there are three SPI controllers, FMC(Firmware Memory Controller), SPI1 and SPI2. The clock source is HCLK. Following is the basic information for ASPEED SPI controller. AST2500: - FMC: CS number: 3 controller reg: 0x1e620000 - 0x1e62ffff decoded address: 0x20000000 - 0x2fffffff - SPI1: CS number: 2 controller reg: 0x1e630000 - 0x1e630fff decoded address: 0x30000000 - 0x37ffffff - SPI2: CS number: 2 controller reg: 0x1e631000 - 0x1e631fff decoded address: 0x38000000 - 0x3fffffff AST2600: - FMC: CS number: 3 controller reg: 0x1e620000 - 0x1e62ffff decoded address: 0x20000000 - 0x2fffffff - SPI1: CS number: 2 controller reg: 0x1e630000 - 0x1e630fff decoded address: 0x30000000 - 0x3fffffff - SPI2: CS number: 3 controller reg: 0x1e631000 - 0x1e631fff decoded address: 0x50000000 - 0x5fffffff Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
2022-08-19 09:01:07 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
status = "disabled";
};
arm: dts: aspeed: Update SPI flash node settings For both AST2500 and AST2600, there are three SPI controllers, FMC(Firmware Memory Controller), SPI1 and SPI2. The clock source is HCLK. Following is the basic information for ASPEED SPI controller. AST2500: - FMC: CS number: 3 controller reg: 0x1e620000 - 0x1e62ffff decoded address: 0x20000000 - 0x2fffffff - SPI1: CS number: 2 controller reg: 0x1e630000 - 0x1e630fff decoded address: 0x30000000 - 0x37ffffff - SPI2: CS number: 2 controller reg: 0x1e631000 - 0x1e631fff decoded address: 0x38000000 - 0x3fffffff AST2600: - FMC: CS number: 3 controller reg: 0x1e620000 - 0x1e62ffff decoded address: 0x20000000 - 0x2fffffff - SPI1: CS number: 2 controller reg: 0x1e630000 - 0x1e630fff decoded address: 0x30000000 - 0x3fffffff - SPI2: CS number: 3 controller reg: 0x1e631000 - 0x1e631fff decoded address: 0x50000000 - 0x5fffffff Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
2022-08-19 09:01:07 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
flash@2 {
reg = < 2 >;
compatible = "jedec,spi-nor";
status = "disabled";
};
};
spi1: flash-controller@1e630000 {
arm: dts: aspeed: Update SPI flash node settings For both AST2500 and AST2600, there are three SPI controllers, FMC(Firmware Memory Controller), SPI1 and SPI2. The clock source is HCLK. Following is the basic information for ASPEED SPI controller. AST2500: - FMC: CS number: 3 controller reg: 0x1e620000 - 0x1e62ffff decoded address: 0x20000000 - 0x2fffffff - SPI1: CS number: 2 controller reg: 0x1e630000 - 0x1e630fff decoded address: 0x30000000 - 0x37ffffff - SPI2: CS number: 2 controller reg: 0x1e631000 - 0x1e631fff decoded address: 0x38000000 - 0x3fffffff AST2600: - FMC: CS number: 3 controller reg: 0x1e620000 - 0x1e62ffff decoded address: 0x20000000 - 0x2fffffff - SPI1: CS number: 2 controller reg: 0x1e630000 - 0x1e630fff decoded address: 0x30000000 - 0x3fffffff - SPI2: CS number: 3 controller reg: 0x1e631000 - 0x1e631fff decoded address: 0x50000000 - 0x5fffffff Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
2022-08-19 09:01:07 +00:00
reg = <0x1e630000 0xc4>, <0x30000000 0x08000000>;
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-spi";
arm: dts: aspeed: Update SPI flash node settings For both AST2500 and AST2600, there are three SPI controllers, FMC(Firmware Memory Controller), SPI1 and SPI2. The clock source is HCLK. Following is the basic information for ASPEED SPI controller. AST2500: - FMC: CS number: 3 controller reg: 0x1e620000 - 0x1e62ffff decoded address: 0x20000000 - 0x2fffffff - SPI1: CS number: 2 controller reg: 0x1e630000 - 0x1e630fff decoded address: 0x30000000 - 0x37ffffff - SPI2: CS number: 2 controller reg: 0x1e631000 - 0x1e631fff decoded address: 0x38000000 - 0x3fffffff AST2600: - FMC: CS number: 3 controller reg: 0x1e620000 - 0x1e62ffff decoded address: 0x20000000 - 0x2fffffff - SPI1: CS number: 2 controller reg: 0x1e630000 - 0x1e630fff decoded address: 0x30000000 - 0x3fffffff - SPI2: CS number: 3 controller reg: 0x1e631000 - 0x1e631fff decoded address: 0x50000000 - 0x5fffffff Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
2022-08-19 09:01:07 +00:00
clocks = <&scu ASPEED_CLK_AHB>;
num-cs = <2>;
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
status = "disabled";
arm: dts: aspeed: Update SPI flash node settings For both AST2500 and AST2600, there are three SPI controllers, FMC(Firmware Memory Controller), SPI1 and SPI2. The clock source is HCLK. Following is the basic information for ASPEED SPI controller. AST2500: - FMC: CS number: 3 controller reg: 0x1e620000 - 0x1e62ffff decoded address: 0x20000000 - 0x2fffffff - SPI1: CS number: 2 controller reg: 0x1e630000 - 0x1e630fff decoded address: 0x30000000 - 0x37ffffff - SPI2: CS number: 2 controller reg: 0x1e631000 - 0x1e631fff decoded address: 0x38000000 - 0x3fffffff AST2600: - FMC: CS number: 3 controller reg: 0x1e620000 - 0x1e62ffff decoded address: 0x20000000 - 0x2fffffff - SPI1: CS number: 2 controller reg: 0x1e630000 - 0x1e630fff decoded address: 0x30000000 - 0x3fffffff - SPI2: CS number: 3 controller reg: 0x1e631000 - 0x1e631fff decoded address: 0x50000000 - 0x5fffffff Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
2022-08-19 09:01:07 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
status = "disabled";
};
arm: dts: aspeed: Update SPI flash node settings For both AST2500 and AST2600, there are three SPI controllers, FMC(Firmware Memory Controller), SPI1 and SPI2. The clock source is HCLK. Following is the basic information for ASPEED SPI controller. AST2500: - FMC: CS number: 3 controller reg: 0x1e620000 - 0x1e62ffff decoded address: 0x20000000 - 0x2fffffff - SPI1: CS number: 2 controller reg: 0x1e630000 - 0x1e630fff decoded address: 0x30000000 - 0x37ffffff - SPI2: CS number: 2 controller reg: 0x1e631000 - 0x1e631fff decoded address: 0x38000000 - 0x3fffffff AST2600: - FMC: CS number: 3 controller reg: 0x1e620000 - 0x1e62ffff decoded address: 0x20000000 - 0x2fffffff - SPI1: CS number: 2 controller reg: 0x1e630000 - 0x1e630fff decoded address: 0x30000000 - 0x3fffffff - SPI2: CS number: 3 controller reg: 0x1e631000 - 0x1e631fff decoded address: 0x50000000 - 0x5fffffff Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
2022-08-19 09:01:07 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
status = "disabled";
};
};
spi2: flash-controller@1e631000 {
arm: dts: aspeed: Update SPI flash node settings For both AST2500 and AST2600, there are three SPI controllers, FMC(Firmware Memory Controller), SPI1 and SPI2. The clock source is HCLK. Following is the basic information for ASPEED SPI controller. AST2500: - FMC: CS number: 3 controller reg: 0x1e620000 - 0x1e62ffff decoded address: 0x20000000 - 0x2fffffff - SPI1: CS number: 2 controller reg: 0x1e630000 - 0x1e630fff decoded address: 0x30000000 - 0x37ffffff - SPI2: CS number: 2 controller reg: 0x1e631000 - 0x1e631fff decoded address: 0x38000000 - 0x3fffffff AST2600: - FMC: CS number: 3 controller reg: 0x1e620000 - 0x1e62ffff decoded address: 0x20000000 - 0x2fffffff - SPI1: CS number: 2 controller reg: 0x1e630000 - 0x1e630fff decoded address: 0x30000000 - 0x3fffffff - SPI2: CS number: 3 controller reg: 0x1e631000 - 0x1e631fff decoded address: 0x50000000 - 0x5fffffff Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
2022-08-19 09:01:07 +00:00
reg = <0x1e631000 0xc4>, <0x38000000 0x08000000>;
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-spi";
arm: dts: aspeed: Update SPI flash node settings For both AST2500 and AST2600, there are three SPI controllers, FMC(Firmware Memory Controller), SPI1 and SPI2. The clock source is HCLK. Following is the basic information for ASPEED SPI controller. AST2500: - FMC: CS number: 3 controller reg: 0x1e620000 - 0x1e62ffff decoded address: 0x20000000 - 0x2fffffff - SPI1: CS number: 2 controller reg: 0x1e630000 - 0x1e630fff decoded address: 0x30000000 - 0x37ffffff - SPI2: CS number: 2 controller reg: 0x1e631000 - 0x1e631fff decoded address: 0x38000000 - 0x3fffffff AST2600: - FMC: CS number: 3 controller reg: 0x1e620000 - 0x1e62ffff decoded address: 0x20000000 - 0x2fffffff - SPI1: CS number: 2 controller reg: 0x1e630000 - 0x1e630fff decoded address: 0x30000000 - 0x3fffffff - SPI2: CS number: 3 controller reg: 0x1e631000 - 0x1e631fff decoded address: 0x50000000 - 0x5fffffff Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
2022-08-19 09:01:07 +00:00
clocks = <&scu ASPEED_CLK_AHB>;
num-cs = <2>;
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
status = "disabled";
arm: dts: aspeed: Update SPI flash node settings For both AST2500 and AST2600, there are three SPI controllers, FMC(Firmware Memory Controller), SPI1 and SPI2. The clock source is HCLK. Following is the basic information for ASPEED SPI controller. AST2500: - FMC: CS number: 3 controller reg: 0x1e620000 - 0x1e62ffff decoded address: 0x20000000 - 0x2fffffff - SPI1: CS number: 2 controller reg: 0x1e630000 - 0x1e630fff decoded address: 0x30000000 - 0x37ffffff - SPI2: CS number: 2 controller reg: 0x1e631000 - 0x1e631fff decoded address: 0x38000000 - 0x3fffffff AST2600: - FMC: CS number: 3 controller reg: 0x1e620000 - 0x1e62ffff decoded address: 0x20000000 - 0x2fffffff - SPI1: CS number: 2 controller reg: 0x1e630000 - 0x1e630fff decoded address: 0x30000000 - 0x3fffffff - SPI2: CS number: 3 controller reg: 0x1e631000 - 0x1e631fff decoded address: 0x50000000 - 0x5fffffff Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
2022-08-19 09:01:07 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
status = "disabled";
};
arm: dts: aspeed: Update SPI flash node settings For both AST2500 and AST2600, there are three SPI controllers, FMC(Firmware Memory Controller), SPI1 and SPI2. The clock source is HCLK. Following is the basic information for ASPEED SPI controller. AST2500: - FMC: CS number: 3 controller reg: 0x1e620000 - 0x1e62ffff decoded address: 0x20000000 - 0x2fffffff - SPI1: CS number: 2 controller reg: 0x1e630000 - 0x1e630fff decoded address: 0x30000000 - 0x37ffffff - SPI2: CS number: 2 controller reg: 0x1e631000 - 0x1e631fff decoded address: 0x38000000 - 0x3fffffff AST2600: - FMC: CS number: 3 controller reg: 0x1e620000 - 0x1e62ffff decoded address: 0x20000000 - 0x2fffffff - SPI1: CS number: 2 controller reg: 0x1e630000 - 0x1e630fff decoded address: 0x30000000 - 0x3fffffff - SPI2: CS number: 3 controller reg: 0x1e631000 - 0x1e631fff decoded address: 0x50000000 - 0x5fffffff Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
2022-08-19 09:01:07 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
status = "disabled";
};
};
aspeed: Add basic ast2500-specific drivers and configuration Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-18 21:44:56 +00:00
vic: interrupt-controller@1e6c0080 {
compatible = "aspeed,ast2400-vic";
interrupt-controller;
#interrupt-cells = <1>;
valid-sources = <0xfefff7ff 0x0807ffff>;
reg = <0x1e6c0080 0x80>;
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
mac0: ethernet@1e660000 {
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
reg = <0x1e660000 0x180>;
interrupts = <2>;
status = "disabled";
};
mac1: ethernet@1e680000 {
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
reg = <0x1e680000 0x180>;
interrupts = <3>;
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
status = "disabled";
};
ehci0: usb@1e6a1000 {
compatible = "aspeed,ast2500-ehci", "generic-ehci";
reg = <0x1e6a1000 0x100>;
interrupts = <5>;
status = "disabled";
};
ehci1: usb@1e6a3000 {
compatible = "aspeed,ast2500-ehci", "generic-ehci";
reg = <0x1e6a3000 0x100>;
interrupts = <13>;
status = "disabled";
};
uhci: usb@1e6b0000 {
compatible = "aspeed,ast2500-uhci", "generic-uhci";
reg = <0x1e6b0000 0x100>;
interrupts = <14>;
#ports = <2>;
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
status = "disabled";
};
aspeed: Add basic ast2500-specific drivers and configuration Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-18 21:44:56 +00:00
apb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
syscon: syscon@1e6e2000 {
compatible = "aspeed,g5-scu", "syscon", "simple-mfd";
reg = <0x1e6e2000 0x1a8>;
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
#clock-cells = <1>;
#reset-cells = <1>;
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
pinctrl: pinctrl {
compatible = "aspeed,g5-pinctrl";
aspeed,external-nodes = <&gfx &lhc>;
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
};
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
rng: hwrng@1e6e2078 {
compatible = "timeriomem_rng";
reg = <0x1e6e2078 0x4>;
period = <1>;
quality = <100>;
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
gfx: display@1e6e6000 {
compatible = "aspeed,ast2500-gfx", "syscon";
reg = <0x1e6e6000 0x1000>;
reg-io-width = <4>;
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
adc: adc@1e6e9000 {
compatible = "aspeed,ast2500-adc";
reg = <0x1e6e9000 0xb0>;
#io-channel-cells = <1>;
status = "disabled";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
sram@1e720000 {
compatible = "mmio-sram";
reg = <0x1e720000 0x9000>; // 36K
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
ARM: dts: ast2500: Update SDHCI nodes Match the description used by the Linux kernel, except use scu instead of syscon as the phandle. Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-06-23 09:05:29 +00:00
sdmmc: sd-controller@1e740000 {
compatible = "aspeed,ast2500-sd-controller";
reg = <0x1e740000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1e740000 0x10000>;
clocks = <&scu ASPEED_CLK_GATE_SDCLK>;
status = "disabled";
sdhci0: sdhci@100 {
compatible = "aspeed,ast2500-sdhci";
reg = <0x100 0x100>;
interrupts = <26>;
sdhci,auto-cmd12;
clocks = <&scu ASPEED_CLK_SDIO>;
status = "disabled";
};
sdhci1: sdhci@200 {
compatible = "aspeed,ast2500-sdhci";
reg = <0x200 0x100>;
interrupts = <26>;
sdhci,auto-cmd12;
clocks = <&scu ASPEED_CLK_SDIO>;
status = "disabled";
};
};
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
gpio: gpio@1e780000 {
#gpio-cells = <2>;
gpio-controller;
compatible = "aspeed,ast2500-gpio";
reg = <0x1e780000 0x1000>;
interrupts = <20>;
gpio-ranges = <&pinctrl 0 0 220>;
ARM: dts: ast2500: Add ngpios property to GPIO node Populate gpio_count in the gpio subsystem for the AST2500. Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
2022-02-15 23:56:57 +00:00
ngpios = <228>;
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
interrupt-controller;
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
timer: timer@1e782000 {
/* This timer is a Faraday FTTMR010 derivative */
compatible = "aspeed,ast2400-timer";
reg = <0x1e782000 0x90>;
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
uart1: serial@1e783000 {
compatible = "ns16550a";
reg = <0x1e783000 0x20>;
reg-shift = <2>;
interrupts = <9>;
no-loopback-test;
status = "disabled";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
uart5: serial@1e784000 {
compatible = "ns16550a";
reg = <0x1e784000 0x20>;
reg-shift = <2>;
interrupts = <10>;
no-loopback-test;
status = "disabled";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
wdt1: watchdog@1e785000 {
compatible = "aspeed,wdt";
reg = <0x1e785000 0x1c>;
interrupts = <27>;
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
wdt2: watchdog@1e785020 {
compatible = "aspeed,wdt";
reg = <0x1e785020 0x1c>;
interrupts = <27>;
status = "disabled";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
wdt3: watchdog@1e785040 {
compatible = "aspeed,wdt";
reg = <0x1e785040 0x1c>;
status = "disabled";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pwm_tacho: pwm-tacho-controller@1e786000 {
compatible = "aspeed,ast2500-pwm-tacho";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1e786000 0x1000>;
status = "disabled";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
vuart: serial@1e787000 {
compatible = "aspeed,ast2500-vuart";
reg = <0x1e787000 0x40>;
reg-shift = <2>;
interrupts = <8>;
no-loopback-test;
status = "disabled";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
lpc: lpc@1e789000 {
compatible = "aspeed,ast2500-lpc", "simple-mfd";
reg = <0x1e789000 0x1000>;
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1e789000 0x1000>;
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
lpc_bmc: lpc-bmc@0 {
compatible = "aspeed,ast2500-lpc-bmc";
reg = <0x0 0x80>;
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
lpc_host: lpc-host@80 {
compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
reg = <0x80 0x1e0>;
reg-io-width = <4>;
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x80 0x1e0>;
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
lpc_ctrl: lpc-ctrl@0 {
compatible = "aspeed,ast2500-lpc-ctrl";
reg = <0x0 0x80>;
status = "disabled";
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
};
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
lpc_snoop: lpc-snoop@0 {
compatible = "aspeed,ast2500-lpc-snoop";
reg = <0x0 0x80>;
interrupts = <8>;
status = "disabled";
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
};
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
lhc: lhc@20 {
compatible = "aspeed,ast2500-lhc";
reg = <0x20 0x24 0x48 0x8>;
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
};
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
lpc_reset: reset-controller@18 {
compatible = "aspeed,ast2500-lpc-reset";
reg = <0x18 0x4>;
#reset-cells = <1>;
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
};
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
ibt: ibt@c0 {
compatible = "aspeed,ast2500-ibt-bmc";
reg = <0xc0 0x18>;
interrupts = <8>;
status = "disabled";
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
};
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
};
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
uart2: serial@1e78d000 {
compatible = "ns16550a";
reg = <0x1e78d000 0x20>;
reg-shift = <2>;
interrupts = <32>;
no-loopback-test;
status = "disabled";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
uart3: serial@1e78e000 {
compatible = "ns16550a";
reg = <0x1e78e000 0x20>;
reg-shift = <2>;
interrupts = <33>;
no-loopback-test;
status = "disabled";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
uart4: serial@1e78f000 {
compatible = "ns16550a";
reg = <0x1e78f000 0x20>;
reg-shift = <2>;
interrupts = <34>;
no-loopback-test;
status = "disabled";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
i2c: i2c@1e78a000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1e78a000 0x1000>;
};
};
};
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
&i2c {
i2c_ic: interrupt-controller@0 {
#interrupt-cells = <1>;
compatible = "aspeed,ast2500-i2c-ic";
reg = <0x0 0x40>;
interrupts = <12>;
interrupt-controller;
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
i2c0: i2c-bus@40 {
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
reg = <0x40 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
bus-frequency = <100000>;
interrupts = <0>;
interrupt-parent = <&i2c_ic>;
status = "disabled";
/* Does not need pinctrl properties */
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
i2c1: i2c-bus@80 {
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
reg = <0x80 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
bus-frequency = <100000>;
interrupts = <1>;
interrupt-parent = <&i2c_ic>;
status = "disabled";
/* Does not need pinctrl properties */
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
i2c2: i2c-bus@c0 {
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
reg = <0xc0 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
bus-frequency = <100000>;
interrupts = <2>;
interrupt-parent = <&i2c_ic>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3_default>;
status = "disabled";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
i2c3: i2c-bus@100 {
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
reg = <0x100 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
bus-frequency = <100000>;
interrupts = <3>;
interrupt-parent = <&i2c_ic>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4_default>;
status = "disabled";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
i2c4: i2c-bus@140 {
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
reg = <0x140 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
bus-frequency = <100000>;
interrupts = <4>;
interrupt-parent = <&i2c_ic>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c5_default>;
status = "disabled";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
i2c5: i2c-bus@180 {
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
reg = <0x180 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
bus-frequency = <100000>;
interrupts = <5>;
interrupt-parent = <&i2c_ic>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c6_default>;
status = "disabled";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
i2c6: i2c-bus@1c0 {
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
reg = <0x1c0 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
bus-frequency = <100000>;
interrupts = <6>;
interrupt-parent = <&i2c_ic>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c7_default>;
status = "disabled";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
i2c7: i2c-bus@300 {
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
reg = <0x300 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
bus-frequency = <100000>;
interrupts = <7>;
interrupt-parent = <&i2c_ic>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c8_default>;
status = "disabled";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
i2c8: i2c-bus@340 {
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
reg = <0x340 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
bus-frequency = <100000>;
interrupts = <8>;
interrupt-parent = <&i2c_ic>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c9_default>;
status = "disabled";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
i2c9: i2c-bus@380 {
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
reg = <0x380 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
bus-frequency = <100000>;
interrupts = <9>;
interrupt-parent = <&i2c_ic>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c10_default>;
status = "disabled";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
i2c10: i2c-bus@3c0 {
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
reg = <0x3c0 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
bus-frequency = <100000>;
interrupts = <10>;
interrupt-parent = <&i2c_ic>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c11_default>;
status = "disabled";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
i2c11: i2c-bus@400 {
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
reg = <0x400 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
bus-frequency = <100000>;
interrupts = <11>;
interrupt-parent = <&i2c_ic>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c12_default>;
status = "disabled";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
i2c12: i2c-bus@440 {
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
reg = <0x440 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
bus-frequency = <100000>;
interrupts = <12>;
interrupt-parent = <&i2c_ic>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c13_default>;
status = "disabled";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
i2c13: i2c-bus@480 {
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
reg = <0x480 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
bus-frequency = <100000>;
interrupts = <13>;
interrupt-parent = <&i2c_ic>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c14_default>;
status = "disabled";
};
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
&pinctrl {
pinctrl_acpi_default: acpi_default {
function = "ACPI";
groups = "ACPI";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_adc0_default: adc0_default {
function = "ADC0";
groups = "ADC0";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_adc1_default: adc1_default {
function = "ADC1";
groups = "ADC1";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_adc10_default: adc10_default {
function = "ADC10";
groups = "ADC10";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_adc11_default: adc11_default {
function = "ADC11";
groups = "ADC11";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_adc12_default: adc12_default {
function = "ADC12";
groups = "ADC12";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_adc13_default: adc13_default {
function = "ADC13";
groups = "ADC13";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_adc14_default: adc14_default {
function = "ADC14";
groups = "ADC14";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_adc15_default: adc15_default {
function = "ADC15";
groups = "ADC15";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_adc2_default: adc2_default {
function = "ADC2";
groups = "ADC2";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_adc3_default: adc3_default {
function = "ADC3";
groups = "ADC3";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_adc4_default: adc4_default {
function = "ADC4";
groups = "ADC4";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_adc5_default: adc5_default {
function = "ADC5";
groups = "ADC5";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_adc6_default: adc6_default {
function = "ADC6";
groups = "ADC6";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_adc7_default: adc7_default {
function = "ADC7";
groups = "ADC7";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_adc8_default: adc8_default {
function = "ADC8";
groups = "ADC8";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_adc9_default: adc9_default {
function = "ADC9";
groups = "ADC9";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_bmcint_default: bmcint_default {
function = "BMCINT";
groups = "BMCINT";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_ddcclk_default: ddcclk_default {
function = "DDCCLK";
groups = "DDCCLK";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_ddcdat_default: ddcdat_default {
function = "DDCDAT";
groups = "DDCDAT";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_espi_default: espi_default {
function = "ESPI";
groups = "ESPI";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_fwspics1_default: fwspics1_default {
function = "FWSPICS1";
groups = "FWSPICS1";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_fwspics2_default: fwspics2_default {
function = "FWSPICS2";
groups = "FWSPICS2";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_gpid0_default: gpid0_default {
function = "GPID0";
groups = "GPID0";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_gpid2_default: gpid2_default {
function = "GPID2";
groups = "GPID2";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_gpid4_default: gpid4_default {
function = "GPID4";
groups = "GPID4";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_gpid6_default: gpid6_default {
function = "GPID6";
groups = "GPID6";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_gpie0_default: gpie0_default {
function = "GPIE0";
groups = "GPIE0";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_gpie2_default: gpie2_default {
function = "GPIE2";
groups = "GPIE2";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_gpie4_default: gpie4_default {
function = "GPIE4";
groups = "GPIE4";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_gpie6_default: gpie6_default {
function = "GPIE6";
groups = "GPIE6";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_i2c10_default: i2c10_default {
function = "I2C10";
groups = "I2C10";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_i2c11_default: i2c11_default {
function = "I2C11";
groups = "I2C11";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_i2c12_default: i2c12_default {
function = "I2C12";
groups = "I2C12";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_i2c13_default: i2c13_default {
function = "I2C13";
groups = "I2C13";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_i2c14_default: i2c14_default {
function = "I2C14";
groups = "I2C14";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_i2c3_default: i2c3_default {
function = "I2C3";
groups = "I2C3";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_i2c4_default: i2c4_default {
function = "I2C4";
groups = "I2C4";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_i2c5_default: i2c5_default {
function = "I2C5";
groups = "I2C5";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_i2c6_default: i2c6_default {
function = "I2C6";
groups = "I2C6";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_i2c7_default: i2c7_default {
function = "I2C7";
groups = "I2C7";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_i2c8_default: i2c8_default {
function = "I2C8";
groups = "I2C8";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_i2c9_default: i2c9_default {
function = "I2C9";
groups = "I2C9";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_lad0_default: lad0_default {
function = "LAD0";
groups = "LAD0";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_lad1_default: lad1_default {
function = "LAD1";
groups = "LAD1";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_lad2_default: lad2_default {
function = "LAD2";
groups = "LAD2";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_lad3_default: lad3_default {
function = "LAD3";
groups = "LAD3";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_lclk_default: lclk_default {
function = "LCLK";
groups = "LCLK";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_lframe_default: lframe_default {
function = "LFRAME";
groups = "LFRAME";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_lpchc_default: lpchc_default {
function = "LPCHC";
groups = "LPCHC";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_lpcpd_default: lpcpd_default {
function = "LPCPD";
groups = "LPCPD";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_lpcplus_default: lpcplus_default {
function = "LPCPLUS";
groups = "LPCPLUS";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_lpcpme_default: lpcpme_default {
function = "LPCPME";
groups = "LPCPME";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_lpcrst_default: lpcrst_default {
function = "LPCRST";
groups = "LPCRST";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_lpcsmi_default: lpcsmi_default {
function = "LPCSMI";
groups = "LPCSMI";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_lsirq_default: lsirq_default {
function = "LSIRQ";
groups = "LSIRQ";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_mac1link_default: mac1link_default {
function = "MAC1LINK";
groups = "MAC1LINK";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_mac2link_default: mac2link_default {
function = "MAC2LINK";
groups = "MAC2LINK";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_mdio1_default: mdio1_default {
function = "MDIO1";
groups = "MDIO1";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_mdio2_default: mdio2_default {
function = "MDIO2";
groups = "MDIO2";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_ncts1_default: ncts1_default {
function = "NCTS1";
groups = "NCTS1";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_ncts2_default: ncts2_default {
function = "NCTS2";
groups = "NCTS2";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_ncts3_default: ncts3_default {
function = "NCTS3";
groups = "NCTS3";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_ncts4_default: ncts4_default {
function = "NCTS4";
groups = "NCTS4";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_ndcd1_default: ndcd1_default {
function = "NDCD1";
groups = "NDCD1";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_ndcd2_default: ndcd2_default {
function = "NDCD2";
groups = "NDCD2";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_ndcd3_default: ndcd3_default {
function = "NDCD3";
groups = "NDCD3";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_ndcd4_default: ndcd4_default {
function = "NDCD4";
groups = "NDCD4";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_ndsr1_default: ndsr1_default {
function = "NDSR1";
groups = "NDSR1";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_ndsr2_default: ndsr2_default {
function = "NDSR2";
groups = "NDSR2";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_ndsr3_default: ndsr3_default {
function = "NDSR3";
groups = "NDSR3";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_ndsr4_default: ndsr4_default {
function = "NDSR4";
groups = "NDSR4";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_ndtr1_default: ndtr1_default {
function = "NDTR1";
groups = "NDTR1";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_ndtr2_default: ndtr2_default {
function = "NDTR2";
groups = "NDTR2";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_ndtr3_default: ndtr3_default {
function = "NDTR3";
groups = "NDTR3";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_ndtr4_default: ndtr4_default {
function = "NDTR4";
groups = "NDTR4";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_nri1_default: nri1_default {
function = "NRI1";
groups = "NRI1";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_nri2_default: nri2_default {
function = "NRI2";
groups = "NRI2";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_nri3_default: nri3_default {
function = "NRI3";
groups = "NRI3";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_nri4_default: nri4_default {
function = "NRI4";
groups = "NRI4";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_nrts1_default: nrts1_default {
function = "NRTS1";
groups = "NRTS1";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_nrts2_default: nrts2_default {
function = "NRTS2";
groups = "NRTS2";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_nrts3_default: nrts3_default {
function = "NRTS3";
groups = "NRTS3";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_nrts4_default: nrts4_default {
function = "NRTS4";
groups = "NRTS4";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_oscclk_default: oscclk_default {
function = "OSCCLK";
groups = "OSCCLK";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_pewake_default: pewake_default {
function = "PEWAKE";
groups = "PEWAKE";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_pnor_default: pnor_default {
function = "PNOR";
groups = "PNOR";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_pwm0_default: pwm0_default {
function = "PWM0";
groups = "PWM0";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_pwm1_default: pwm1_default {
function = "PWM1";
groups = "PWM1";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_pwm2_default: pwm2_default {
function = "PWM2";
groups = "PWM2";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_pwm3_default: pwm3_default {
function = "PWM3";
groups = "PWM3";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_pwm4_default: pwm4_default {
function = "PWM4";
groups = "PWM4";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_pwm5_default: pwm5_default {
function = "PWM5";
groups = "PWM5";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_pwm6_default: pwm6_default {
function = "PWM6";
groups = "PWM6";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_pwm7_default: pwm7_default {
function = "PWM7";
groups = "PWM7";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_rgmii1_default: rgmii1_default {
function = "RGMII1";
groups = "RGMII1";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_rgmii2_default: rgmii2_default {
function = "RGMII2";
groups = "RGMII2";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_rmii1_default: rmii1_default {
function = "RMII1";
groups = "RMII1";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_rmii2_default: rmii2_default {
function = "RMII2";
groups = "RMII2";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_rxd1_default: rxd1_default {
function = "RXD1";
groups = "RXD1";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_rxd2_default: rxd2_default {
function = "RXD2";
groups = "RXD2";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_rxd3_default: rxd3_default {
function = "RXD3";
groups = "RXD3";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_rxd4_default: rxd4_default {
function = "RXD4";
groups = "RXD4";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_salt1_default: salt1_default {
function = "SALT1";
groups = "SALT1";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_salt10_default: salt10_default {
function = "SALT10";
groups = "SALT10";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_salt11_default: salt11_default {
function = "SALT11";
groups = "SALT11";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_salt12_default: salt12_default {
function = "SALT12";
groups = "SALT12";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_salt13_default: salt13_default {
function = "SALT13";
groups = "SALT13";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_salt14_default: salt14_default {
function = "SALT14";
groups = "SALT14";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_salt2_default: salt2_default {
function = "SALT2";
groups = "SALT2";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_salt3_default: salt3_default {
function = "SALT3";
groups = "SALT3";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_salt4_default: salt4_default {
function = "SALT4";
groups = "SALT4";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_salt5_default: salt5_default {
function = "SALT5";
groups = "SALT5";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_salt6_default: salt6_default {
function = "SALT6";
groups = "SALT6";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_salt7_default: salt7_default {
function = "SALT7";
groups = "SALT7";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_salt8_default: salt8_default {
function = "SALT8";
groups = "SALT8";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_salt9_default: salt9_default {
function = "SALT9";
groups = "SALT9";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_scl1_default: scl1_default {
function = "SCL1";
groups = "SCL1";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_scl2_default: scl2_default {
function = "SCL2";
groups = "SCL2";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_sd1_default: sd1_default {
function = "SD1";
groups = "SD1";
};
aspeed: Add basic ast2500-specific drivers and configuration Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-18 21:44:56 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_sd2_default: sd2_default {
function = "SD2";
groups = "SD2";
};
aspeed: Add basic ast2500-specific drivers and configuration Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-18 21:44:56 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_sda1_default: sda1_default {
function = "SDA1";
groups = "SDA1";
};
aspeed: Add basic ast2500-specific drivers and configuration Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-18 21:44:56 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_sda2_default: sda2_default {
function = "SDA2";
groups = "SDA2";
};
aspeed: Add basic ast2500-specific drivers and configuration Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-18 21:44:56 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_sgps1_default: sgps1_default {
function = "SGPS1";
groups = "SGPS1";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_sgps2_default: sgps2_default {
function = "SGPS2";
groups = "SGPS2";
};
aspeed: Add basic ast2500-specific drivers and configuration Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-18 21:44:56 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_sioonctrl_default: sioonctrl_default {
function = "SIOONCTRL";
groups = "SIOONCTRL";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_siopbi_default: siopbi_default {
function = "SIOPBI";
groups = "SIOPBI";
};
aspeed: Add basic ast2500-specific drivers and configuration Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-18 21:44:56 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_siopbo_default: siopbo_default {
function = "SIOPBO";
groups = "SIOPBO";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_siopwreq_default: siopwreq_default {
function = "SIOPWREQ";
groups = "SIOPWREQ";
};
aspeed: Add basic ast2500-specific drivers and configuration Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-18 21:44:56 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_siopwrgd_default: siopwrgd_default {
function = "SIOPWRGD";
groups = "SIOPWRGD";
};
aspeed: Add basic ast2500-specific drivers and configuration Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-18 21:44:56 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_sios3_default: sios3_default {
function = "SIOS3";
groups = "SIOS3";
};
aspeed: Add basic ast2500-specific drivers and configuration Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-18 21:44:56 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_sios5_default: sios5_default {
function = "SIOS5";
groups = "SIOS5";
};
aspeed: Add basic ast2500-specific drivers and configuration Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-18 21:44:56 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_siosci_default: siosci_default {
function = "SIOSCI";
groups = "SIOSCI";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_spi1_default: spi1_default {
function = "SPI1";
groups = "SPI1";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_spi1cs1_default: spi1cs1_default {
function = "SPI1CS1";
groups = "SPI1CS1";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_spi1debug_default: spi1debug_default {
function = "SPI1DEBUG";
groups = "SPI1DEBUG";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_spi1passthru_default: spi1passthru_default {
function = "SPI1PASSTHRU";
groups = "SPI1PASSTHRU";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_spi2ck_default: spi2ck_default {
function = "SPI2CK";
groups = "SPI2CK";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_spi2cs0_default: spi2cs0_default {
function = "SPI2CS0";
groups = "SPI2CS0";
};
aspeed: Update ast2500 Device Tree Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:20 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_spi2cs1_default: spi2cs1_default {
function = "SPI2CS1";
groups = "SPI2CS1";
};
aspeed: Add basic ast2500-specific drivers and configuration Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-18 21:44:56 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_spi2miso_default: spi2miso_default {
function = "SPI2MISO";
groups = "SPI2MISO";
};
aspeed: Add basic ast2500-specific drivers and configuration Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-18 21:44:56 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_spi2mosi_default: spi2mosi_default {
function = "SPI2MOSI";
groups = "SPI2MOSI";
};
aspeed: Add basic ast2500-specific drivers and configuration Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-18 21:44:56 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_timer3_default: timer3_default {
function = "TIMER3";
groups = "TIMER3";
};
aspeed: Add basic ast2500-specific drivers and configuration Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-18 21:44:56 +00:00
aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level This is a large update of the AST2500 SoC DTS file bringing it to the level of commit 927c2fc2db19 : Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register address There are some differences on the compatibility property names. scu, reset and clock drivers are also different. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-29 06:06:39 +00:00
pinctrl_timer4_default: timer4_default {
function = "TIMER4";
groups = "TIMER4";
};
pinctrl_timer5_default: timer5_default {
function = "TIMER5";
groups = "TIMER5";
};
pinctrl_timer6_default: timer6_default {
function = "TIMER6";
groups = "TIMER6";
};
pinctrl_timer7_default: timer7_default {
function = "TIMER7";
groups = "TIMER7";
};
pinctrl_timer8_default: timer8_default {
function = "TIMER8";
groups = "TIMER8";
};
pinctrl_txd1_default: txd1_default {
function = "TXD1";
groups = "TXD1";
};
pinctrl_txd2_default: txd2_default {
function = "TXD2";
groups = "TXD2";
};
pinctrl_txd3_default: txd3_default {
function = "TXD3";
groups = "TXD3";
};
pinctrl_txd4_default: txd4_default {
function = "TXD4";
groups = "TXD4";
};
pinctrl_uart6_default: uart6_default {
function = "UART6";
groups = "UART6";
};
pinctrl_usbcki_default: usbcki_default {
function = "USBCKI";
groups = "USBCKI";
};
pinctrl_usb2ah_default: usb2ah_default {
function = "USB2AH";
groups = "USB2AH";
};
pinctrl_usb11bhid_default: usb11bhid_default {
function = "USB11BHID";
groups = "USB11BHID";
};
pinctrl_usb2bh_default: usb2bh_default {
function = "USB2BH";
groups = "USB2BH";
};
pinctrl_vgabiosrom_default: vgabiosrom_default {
function = "VGABIOSROM";
groups = "VGABIOSROM";
};
pinctrl_vgahs_default: vgahs_default {
function = "VGAHS";
groups = "VGAHS";
};
pinctrl_vgavs_default: vgavs_default {
function = "VGAVS";
groups = "VGAVS";
};
pinctrl_vpi24_default: vpi24_default {
function = "VPI24";
groups = "VPI24";
};
pinctrl_vpo_default: vpo_default {
function = "VPO";
groups = "VPO";
};
pinctrl_wdtrst1_default: wdtrst1_default {
function = "WDTRST1";
groups = "WDTRST1";
};
pinctrl_wdtrst2_default: wdtrst2_default {
function = "WDTRST2";
groups = "WDTRST2";
aspeed: Add basic ast2500-specific drivers and configuration Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-18 21:44:56 +00:00
};
};
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