2018-05-06 21:58:06 +00:00
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// SPDX-License-Identifier: GPL-2.0
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2017-05-15 09:49:56 +00:00
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/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd
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* Author: Andy Yan <andy.yan@rock-chips.com>
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2017-06-22 21:47:11 +00:00
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* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
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2017-05-15 09:49:56 +00:00
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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2017-06-22 21:51:37 +00:00
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#include <dt-structs.h>
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2017-05-15 09:49:56 +00:00
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#include <errno.h>
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2020-05-10 17:40:05 +00:00
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#include <log.h>
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2020-02-03 14:36:16 +00:00
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#include <malloc.h>
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2017-06-22 21:51:37 +00:00
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#include <mapmem.h>
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2017-05-15 09:49:56 +00:00
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#include <syscon.h>
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2017-09-20 06:37:50 +00:00
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#include <bitfield.h>
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2019-03-28 03:01:23 +00:00
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#include <asm/arch-rockchip/clock.h>
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#include <asm/arch-rockchip/cru_rk3368.h>
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#include <asm/arch-rockchip/hardware.h>
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2017-05-15 09:49:56 +00:00
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#include <asm/io.h>
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2020-12-23 02:30:28 +00:00
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#include <dm/device-internal.h>
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2017-05-15 09:49:56 +00:00
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#include <dm/lists.h>
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#include <dt-bindings/clock/rk3368-cru.h>
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2020-05-10 17:40:11 +00:00
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#include <linux/delay.h>
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2023-09-15 00:21:46 +00:00
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#include <linux/printk.h>
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2020-05-10 17:40:09 +00:00
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#include <linux/stringify.h>
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2017-05-15 09:49:56 +00:00
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2017-06-22 21:51:37 +00:00
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct rk3368_clk_plat {
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struct dtd_rockchip_rk3368_cru dtd;
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};
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#endif
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2017-05-15 09:49:56 +00:00
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struct pll_div {
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u32 nr;
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u32 nf;
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u32 no;
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};
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#define OSC_HZ (24 * 1000 * 1000)
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#define APLL_L_HZ (800 * 1000 * 1000)
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#define APLL_B_HZ (816 * 1000 * 1000)
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#define GPLL_HZ (576 * 1000 * 1000)
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#define CPLL_HZ (400 * 1000 * 1000)
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#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
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#define PLL_DIVISORS(hz, _nr, _no) { \
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.nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no}; \
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_Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
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(_nr * _no) == hz, #hz "Hz cannot be hit with PLL " \
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"divisors on line " __stringify(__LINE__));
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2017-06-22 21:53:44 +00:00
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#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
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2017-05-15 09:49:56 +00:00
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static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2);
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static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2);
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2017-06-22 21:53:44 +00:00
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#if !defined(CONFIG_TPL_BUILD)
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2017-05-15 09:49:56 +00:00
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static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2);
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static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6);
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2017-06-22 21:53:44 +00:00
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#endif
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#endif
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2017-05-15 09:49:56 +00:00
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2017-07-04 12:49:38 +00:00
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static ulong rk3368_clk_get_rate(struct clk *clk);
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2017-05-15 09:49:56 +00:00
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/* Get pll rate by id */
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static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru,
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enum rk3368_pll_id pll_id)
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{
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uint32_t nr, no, nf;
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uint32_t con;
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struct rk3368_pll *pll = &cru->pll[pll_id];
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con = readl(&pll->con3);
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switch ((con & PLL_MODE_MASK) >> PLL_MODE_SHIFT) {
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case PLL_MODE_SLOW:
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return OSC_HZ;
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case PLL_MODE_NORMAL:
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con = readl(&pll->con0);
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no = ((con & PLL_OD_MASK) >> PLL_OD_SHIFT) + 1;
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nr = ((con & PLL_NR_MASK) >> PLL_NR_SHIFT) + 1;
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con = readl(&pll->con1);
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nf = ((con & PLL_NF_MASK) >> PLL_NF_SHIFT) + 1;
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return (24 * nf / (nr * no)) * 1000000;
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case PLL_MODE_DEEP_SLOW:
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default:
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return 32768;
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}
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}
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2017-06-22 21:53:44 +00:00
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#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
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2017-05-15 09:49:56 +00:00
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static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id,
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2017-06-22 21:47:11 +00:00
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const struct pll_div *div)
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2017-05-15 09:49:56 +00:00
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{
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struct rk3368_pll *pll = &cru->pll[pll_id];
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/* All PLLs have same VCO and output frequency range restrictions*/
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uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
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uint output_hz = vco_hz / div->no;
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debug("PLL at %p: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
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pll, div->nf, div->nr, div->no, vco_hz, output_hz);
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/* enter slow mode and reset pll */
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rk_clrsetreg(&pll->con3, PLL_MODE_MASK | PLL_RESET_MASK,
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PLL_RESET << PLL_RESET_SHIFT);
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rk_clrsetreg(&pll->con0, PLL_NR_MASK | PLL_OD_MASK,
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((div->nr - 1) << PLL_NR_SHIFT) |
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((div->no - 1) << PLL_OD_SHIFT));
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writel((div->nf - 1) << PLL_NF_SHIFT, &pll->con1);
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2017-06-22 21:47:11 +00:00
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/*
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* BWADJ should be set to NF / 2 to ensure the nominal bandwidth.
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* Compare the RK3368 TRM, section "3.6.4 PLL Bandwidth Adjustment".
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*/
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clrsetbits_le32(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
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2017-05-15 09:49:56 +00:00
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udelay(10);
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/* return from reset */
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rk_clrreg(&pll->con3, PLL_RESET_MASK);
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/* waiting for pll lock */
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while (!(readl(&pll->con1) & PLL_LOCK_STA))
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udelay(1);
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rk_clrsetreg(&pll->con3, PLL_MODE_MASK,
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PLL_MODE_NORMAL << PLL_MODE_SHIFT);
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return 0;
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}
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2017-06-22 21:53:44 +00:00
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#endif
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2017-05-15 09:49:56 +00:00
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2017-06-22 21:53:44 +00:00
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#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
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2017-05-15 09:49:56 +00:00
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static void rkclk_init(struct rk3368_cru *cru)
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{
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u32 apllb, aplll, dpll, cpll, gpll;
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2017-06-22 21:47:11 +00:00
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rkclk_set_pll(cru, APLLB, &apll_b_init_cfg);
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rkclk_set_pll(cru, APLLL, &apll_l_init_cfg);
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2017-06-22 21:53:44 +00:00
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#if !defined(CONFIG_TPL_BUILD)
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/*
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* If we plan to return to the boot ROM, we can't increase the
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* GPLL rate from the SPL stage.
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*/
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2017-06-22 21:47:11 +00:00
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rkclk_set_pll(cru, GPLL, &gpll_init_cfg);
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rkclk_set_pll(cru, CPLL, &cpll_init_cfg);
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2017-06-22 21:53:44 +00:00
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#endif
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2017-05-15 09:49:56 +00:00
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apllb = rkclk_pll_get_rate(cru, APLLB);
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aplll = rkclk_pll_get_rate(cru, APLLL);
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dpll = rkclk_pll_get_rate(cru, DPLL);
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cpll = rkclk_pll_get_rate(cru, CPLL);
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gpll = rkclk_pll_get_rate(cru, GPLL);
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debug("%s apllb(%d) apll(%d) dpll(%d) cpll(%d) gpll(%d)\n",
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__func__, apllb, aplll, dpll, cpll, gpll);
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}
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2017-06-22 21:53:44 +00:00
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#endif
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2017-05-15 09:49:56 +00:00
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2021-08-08 18:20:09 +00:00
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#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC)
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2017-05-15 09:49:56 +00:00
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static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id)
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{
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u32 div, con, con_id, rate;
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u32 pll_rate;
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switch (clk_id) {
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2017-07-04 12:49:38 +00:00
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case HCLK_SDMMC:
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2017-05-15 09:49:56 +00:00
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con_id = 50;
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break;
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2017-07-04 12:49:38 +00:00
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case HCLK_EMMC:
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2017-05-15 09:49:56 +00:00
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con_id = 51;
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break;
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case SCLK_SDIO0:
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con_id = 48;
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break;
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default:
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return -EINVAL;
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}
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con = readl(&cru->clksel_con[con_id]);
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2017-07-04 12:49:38 +00:00
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switch (con & MMC_PLL_SEL_MASK) {
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2017-05-15 09:49:56 +00:00
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case MMC_PLL_SEL_GPLL:
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pll_rate = rkclk_pll_get_rate(cru, GPLL);
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break;
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case MMC_PLL_SEL_24M:
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pll_rate = OSC_HZ;
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break;
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case MMC_PLL_SEL_CPLL:
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2017-07-04 12:49:38 +00:00
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pll_rate = rkclk_pll_get_rate(cru, CPLL);
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break;
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2017-05-15 09:49:56 +00:00
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case MMC_PLL_SEL_USBPHY_480M:
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default:
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return -EINVAL;
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}
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div = (con & MMC_CLK_DIV_MASK) >> MMC_CLK_DIV_SHIFT;
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rate = DIV_TO_RATE(pll_rate, div);
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2017-07-04 12:49:38 +00:00
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debug("%s: raw rate %d (post-divide by 2)\n", __func__, rate);
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2017-05-15 09:49:56 +00:00
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return rate >> 1;
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}
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2017-07-04 12:49:38 +00:00
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static ulong rk3368_mmc_find_best_rate_and_parent(struct clk *clk,
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ulong rate,
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u32 *best_mux,
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u32 *best_div)
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{
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int i;
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ulong best_rate = 0;
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const ulong MHz = 1000000;
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const struct {
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u32 mux;
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ulong rate;
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} parents[] = {
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{ .mux = MMC_PLL_SEL_CPLL, .rate = CPLL_HZ },
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{ .mux = MMC_PLL_SEL_GPLL, .rate = GPLL_HZ },
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{ .mux = MMC_PLL_SEL_24M, .rate = 24 * MHz }
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};
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debug("%s: target rate %ld\n", __func__, rate);
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for (i = 0; i < ARRAY_SIZE(parents); ++i) {
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/*
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* Find the largest rate no larger than the target-rate for
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* the current parent.
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*/
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ulong parent_rate = parents[i].rate;
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u32 div = DIV_ROUND_UP(parent_rate, rate);
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u32 adj_div = div;
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ulong new_rate = parent_rate / adj_div;
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debug("%s: rate %ld, parent-mux %d, parent-rate %ld, div %d\n",
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__func__, rate, parents[i].mux, parents[i].rate, div);
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/* Skip, if not representable */
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if ((div - 1) > MMC_CLK_DIV_MASK)
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continue;
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/* Skip, if we already have a better (or equal) solution */
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if (new_rate <= best_rate)
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continue;
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/* This is our new best rate. */
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best_rate = new_rate;
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*best_mux = parents[i].mux;
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*best_div = div - 1;
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}
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debug("%s: best_mux = %x, best_div = %d, best_rate = %ld\n",
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__func__, *best_mux, *best_div, best_rate);
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return best_rate;
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}
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static ulong rk3368_mmc_set_clk(struct clk *clk, ulong rate)
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2017-05-15 09:49:56 +00:00
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{
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2017-07-04 12:49:38 +00:00
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struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
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struct rk3368_cru *cru = priv->cru;
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ulong clk_id = clk->id;
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u32 con_id, mux = 0, div = 0;
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2017-05-15 09:49:56 +00:00
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2017-07-04 12:49:38 +00:00
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/* Find the best parent and rate */
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rk3368_mmc_find_best_rate_and_parent(clk, rate << 1, &mux, &div);
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2017-05-15 09:49:56 +00:00
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switch (clk_id) {
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2017-07-04 12:49:38 +00:00
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case HCLK_SDMMC:
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2017-05-15 09:49:56 +00:00
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con_id = 50;
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break;
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2017-07-04 12:49:38 +00:00
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case HCLK_EMMC:
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2017-05-15 09:49:56 +00:00
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con_id = 51;
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break;
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case SCLK_SDIO0:
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con_id = 48;
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break;
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default:
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return -EINVAL;
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}
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2017-07-04 12:49:38 +00:00
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rk_clrsetreg(&cru->clksel_con[con_id],
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MMC_PLL_SEL_MASK | MMC_CLK_DIV_MASK,
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mux | div);
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2017-05-15 09:49:56 +00:00
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return rk3368_mmc_get_clk(cru, clk_id);
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}
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2017-07-04 12:49:38 +00:00
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#endif
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2017-05-15 09:49:56 +00:00
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2017-07-05 09:55:23 +00:00
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#if IS_ENABLED(CONFIG_TPL_BUILD)
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2017-06-22 22:01:10 +00:00
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static ulong rk3368_ddr_set_clk(struct rk3368_cru *cru, ulong set_rate)
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{
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const struct pll_div *dpll_cfg = NULL;
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const ulong MHz = 1000000;
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/* Fout = ((Fin /NR) * NF )/ NO */
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2017-07-05 09:55:23 +00:00
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static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1);
|
|
|
|
static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1);
|
|
|
|
static const struct pll_div dpll_1600 = PLL_DIVISORS(1600 * MHz, 3, 2);
|
2017-06-22 22:01:10 +00:00
|
|
|
|
|
|
|
switch (set_rate) {
|
|
|
|
case 1200*MHz:
|
|
|
|
dpll_cfg = &dpll_1200;
|
|
|
|
break;
|
|
|
|
case 1332*MHz:
|
|
|
|
dpll_cfg = &dpll_1332;
|
|
|
|
break;
|
|
|
|
case 1600*MHz:
|
|
|
|
dpll_cfg = &dpll_1600;
|
|
|
|
break;
|
|
|
|
default:
|
2017-09-16 05:10:41 +00:00
|
|
|
pr_err("Unsupported SDRAM frequency!,%ld\n", set_rate);
|
2017-06-22 22:01:10 +00:00
|
|
|
}
|
|
|
|
rkclk_set_pll(cru, DPLL, dpll_cfg);
|
|
|
|
|
|
|
|
return set_rate;
|
|
|
|
}
|
2017-07-05 09:55:23 +00:00
|
|
|
#endif
|
2017-06-22 22:01:10 +00:00
|
|
|
|
2017-07-14 17:57:39 +00:00
|
|
|
#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
|
2018-01-13 06:07:04 +00:00
|
|
|
static ulong rk3368_gmac_set_clk(struct rk3368_cru *cru, ulong set_rate)
|
2017-07-14 17:57:39 +00:00
|
|
|
{
|
2018-01-13 06:07:04 +00:00
|
|
|
ulong ret;
|
|
|
|
|
2017-07-14 17:57:39 +00:00
|
|
|
/*
|
2018-01-13 06:07:04 +00:00
|
|
|
* The gmac clock can be derived either from an external clock
|
|
|
|
* or can be generated from internally by a divider from SCLK_MAC.
|
2017-07-14 17:57:39 +00:00
|
|
|
*/
|
2018-01-13 06:07:04 +00:00
|
|
|
if (readl(&cru->clksel_con[43]) & GMAC_MUX_SEL_EXTCLK) {
|
|
|
|
/* An external clock will always generate the right rate... */
|
|
|
|
ret = set_rate;
|
|
|
|
} else {
|
|
|
|
u32 con = readl(&cru->clksel_con[43]);
|
|
|
|
ulong pll_rate;
|
|
|
|
u8 div;
|
|
|
|
|
|
|
|
if (((con >> GMAC_PLL_SHIFT) & GMAC_PLL_MASK) ==
|
|
|
|
GMAC_PLL_SELECT_GENERAL)
|
|
|
|
pll_rate = GPLL_HZ;
|
|
|
|
else if (((con >> GMAC_PLL_SHIFT) & GMAC_PLL_MASK) ==
|
|
|
|
GMAC_PLL_SELECT_CODEC)
|
|
|
|
pll_rate = CPLL_HZ;
|
|
|
|
else
|
|
|
|
/* CPLL is not set */
|
|
|
|
return -EPERM;
|
|
|
|
|
|
|
|
div = DIV_ROUND_UP(pll_rate, set_rate) - 1;
|
|
|
|
if (div <= 0x1f)
|
|
|
|
rk_clrsetreg(&cru->clksel_con[43], GMAC_DIV_CON_MASK,
|
|
|
|
div << GMAC_DIV_CON_SHIFT);
|
|
|
|
else
|
|
|
|
debug("Unsupported div for gmac:%d\n", div);
|
|
|
|
|
|
|
|
return DIV_TO_RATE(pll_rate, div);
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
2017-07-14 17:57:39 +00:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2017-07-25 14:48:16 +00:00
|
|
|
/*
|
|
|
|
* RK3368 SPI clocks have a common divider-width (7 bits) and a single bit
|
|
|
|
* to select either CPLL or GPLL as the clock-parent. The location within
|
|
|
|
* the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable.
|
|
|
|
*/
|
|
|
|
|
|
|
|
struct spi_clkreg {
|
|
|
|
uint8_t reg; /* CLKSEL_CON[reg] register in CRU */
|
|
|
|
uint8_t div_shift;
|
|
|
|
uint8_t sel_shift;
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The entries are numbered relative to their offset from SCLK_SPI0.
|
|
|
|
*/
|
|
|
|
static const struct spi_clkreg spi_clkregs[] = {
|
|
|
|
[0] = { .reg = 45, .div_shift = 0, .sel_shift = 7, },
|
|
|
|
[1] = { .reg = 45, .div_shift = 8, .sel_shift = 15, },
|
|
|
|
[2] = { .reg = 46, .div_shift = 8, .sel_shift = 15, },
|
|
|
|
};
|
|
|
|
|
|
|
|
static inline u32 extract_bits(u32 val, unsigned width, unsigned shift)
|
|
|
|
{
|
|
|
|
return (val >> shift) & ((1 << width) - 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
static ulong rk3368_spi_get_clk(struct rk3368_cru *cru, ulong clk_id)
|
|
|
|
{
|
|
|
|
const struct spi_clkreg *spiclk = NULL;
|
|
|
|
u32 div, val;
|
|
|
|
|
|
|
|
switch (clk_id) {
|
|
|
|
case SCLK_SPI0 ... SCLK_SPI2:
|
|
|
|
spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
2017-09-16 05:10:41 +00:00
|
|
|
pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
|
2017-07-25 14:48:16 +00:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
val = readl(&cru->clksel_con[spiclk->reg]);
|
|
|
|
div = extract_bits(val, 7, spiclk->div_shift);
|
|
|
|
|
|
|
|
debug("%s: div 0x%x\n", __func__, div);
|
|
|
|
return DIV_TO_RATE(GPLL_HZ, div);
|
|
|
|
}
|
|
|
|
|
|
|
|
static ulong rk3368_spi_set_clk(struct rk3368_cru *cru, ulong clk_id, uint hz)
|
|
|
|
{
|
|
|
|
const struct spi_clkreg *spiclk = NULL;
|
|
|
|
int src_clk_div;
|
|
|
|
|
|
|
|
src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz);
|
|
|
|
assert(src_clk_div < 127);
|
|
|
|
|
|
|
|
switch (clk_id) {
|
|
|
|
case SCLK_SPI0 ... SCLK_SPI2:
|
|
|
|
spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
2017-09-16 05:10:41 +00:00
|
|
|
pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
|
2017-07-25 14:48:16 +00:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
rk_clrsetreg(&cru->clksel_con[spiclk->reg],
|
|
|
|
((0x7f << spiclk->div_shift) |
|
|
|
|
(0x1 << spiclk->sel_shift)),
|
|
|
|
((src_clk_div << spiclk->div_shift) |
|
|
|
|
(1 << spiclk->sel_shift)));
|
|
|
|
|
|
|
|
return rk3368_spi_get_clk(cru, clk_id);
|
|
|
|
}
|
|
|
|
|
2017-09-20 06:37:50 +00:00
|
|
|
static ulong rk3368_saradc_get_clk(struct rk3368_cru *cru)
|
|
|
|
{
|
|
|
|
u32 div, val;
|
|
|
|
|
|
|
|
val = readl(&cru->clksel_con[25]);
|
|
|
|
div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
|
|
|
|
CLK_SARADC_DIV_CON_WIDTH);
|
|
|
|
|
|
|
|
return DIV_TO_RATE(OSC_HZ, div);
|
|
|
|
}
|
|
|
|
|
|
|
|
static ulong rk3368_saradc_set_clk(struct rk3368_cru *cru, uint hz)
|
|
|
|
{
|
|
|
|
int src_clk_div;
|
|
|
|
|
|
|
|
src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
|
|
|
|
assert(src_clk_div < 128);
|
|
|
|
|
|
|
|
rk_clrsetreg(&cru->clksel_con[25],
|
|
|
|
CLK_SARADC_DIV_CON_MASK,
|
|
|
|
src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
|
|
|
|
|
|
|
|
return rk3368_saradc_get_clk(cru);
|
|
|
|
}
|
|
|
|
|
2017-07-25 14:48:16 +00:00
|
|
|
static ulong rk3368_clk_get_rate(struct clk *clk)
|
|
|
|
{
|
|
|
|
struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
|
|
|
|
ulong rate = 0;
|
|
|
|
|
|
|
|
debug("%s: id %ld\n", __func__, clk->id);
|
|
|
|
switch (clk->id) {
|
|
|
|
case PLL_CPLL:
|
|
|
|
rate = rkclk_pll_get_rate(priv->cru, CPLL);
|
|
|
|
break;
|
|
|
|
case PLL_GPLL:
|
|
|
|
rate = rkclk_pll_get_rate(priv->cru, GPLL);
|
|
|
|
break;
|
|
|
|
case SCLK_SPI0 ... SCLK_SPI2:
|
|
|
|
rate = rk3368_spi_get_clk(priv->cru, clk->id);
|
|
|
|
break;
|
2021-08-08 18:20:09 +00:00
|
|
|
#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC)
|
2017-07-25 14:48:16 +00:00
|
|
|
case HCLK_SDMMC:
|
|
|
|
case HCLK_EMMC:
|
|
|
|
rate = rk3368_mmc_get_clk(priv->cru, clk->id);
|
|
|
|
break;
|
|
|
|
#endif
|
2017-09-20 06:37:50 +00:00
|
|
|
case SCLK_SARADC:
|
|
|
|
rate = rk3368_saradc_get_clk(priv->cru);
|
|
|
|
break;
|
2017-07-25 14:48:16 +00:00
|
|
|
default:
|
|
|
|
return -ENOENT;
|
|
|
|
}
|
|
|
|
|
|
|
|
return rate;
|
|
|
|
}
|
|
|
|
|
2017-05-15 09:49:56 +00:00
|
|
|
static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
|
|
|
|
{
|
2017-07-05 10:11:58 +00:00
|
|
|
__maybe_unused struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
|
2017-05-15 09:49:56 +00:00
|
|
|
ulong ret = 0;
|
|
|
|
|
|
|
|
debug("%s id:%ld rate:%ld\n", __func__, clk->id, rate);
|
|
|
|
switch (clk->id) {
|
2017-07-25 14:48:16 +00:00
|
|
|
case SCLK_SPI0 ... SCLK_SPI2:
|
|
|
|
ret = rk3368_spi_set_clk(priv->cru, clk->id, rate);
|
|
|
|
break;
|
2017-07-05 09:55:23 +00:00
|
|
|
#if IS_ENABLED(CONFIG_TPL_BUILD)
|
2017-06-22 22:01:10 +00:00
|
|
|
case CLK_DDR:
|
|
|
|
ret = rk3368_ddr_set_clk(priv->cru, rate);
|
|
|
|
break;
|
2017-07-05 09:55:23 +00:00
|
|
|
#endif
|
2021-08-08 18:20:09 +00:00
|
|
|
#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC)
|
2017-07-04 12:49:38 +00:00
|
|
|
case HCLK_SDMMC:
|
|
|
|
case HCLK_EMMC:
|
|
|
|
ret = rk3368_mmc_set_clk(clk, rate);
|
|
|
|
break;
|
|
|
|
#endif
|
2017-07-14 17:57:39 +00:00
|
|
|
#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
|
2017-07-04 12:49:38 +00:00
|
|
|
case SCLK_MAC:
|
2017-07-14 17:57:39 +00:00
|
|
|
/* select the external clock */
|
2018-01-13 06:07:04 +00:00
|
|
|
ret = rk3368_gmac_set_clk(priv->cru, rate);
|
2017-05-15 09:49:56 +00:00
|
|
|
break;
|
2017-07-14 17:57:39 +00:00
|
|
|
#endif
|
2017-09-20 06:37:50 +00:00
|
|
|
case SCLK_SARADC:
|
|
|
|
ret = rk3368_saradc_set_clk(priv->cru, rate);
|
|
|
|
break;
|
2017-05-15 09:49:56 +00:00
|
|
|
default:
|
|
|
|
return -ENOENT;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2018-01-25 14:27:10 +00:00
|
|
|
static int __maybe_unused rk3368_gmac_set_parent(struct clk *clk, struct clk *parent)
|
2018-01-13 06:07:04 +00:00
|
|
|
{
|
|
|
|
struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
|
|
|
|
struct rk3368_cru *cru = priv->cru;
|
|
|
|
const char *clock_output_name;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If the requested parent is in the same clock-controller and
|
|
|
|
* the id is SCLK_MAC ("sclk_mac"), switch to the internal
|
|
|
|
* clock.
|
|
|
|
*/
|
|
|
|
if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC)) {
|
|
|
|
debug("%s: switching GAMC to SCLK_MAC\n", __func__);
|
|
|
|
rk_clrreg(&cru->clksel_con[43], GMAC_MUX_SEL_EXTCLK);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Otherwise, we need to check the clock-output-names of the
|
|
|
|
* requested parent to see if the requested id is "ext_gmac".
|
|
|
|
*/
|
|
|
|
ret = dev_read_string_index(parent->dev, "clock-output-names",
|
|
|
|
parent->id, &clock_output_name);
|
|
|
|
if (ret < 0)
|
|
|
|
return -ENODATA;
|
|
|
|
|
|
|
|
/* If this is "ext_gmac", switch to the external clock input */
|
|
|
|
if (!strcmp(clock_output_name, "ext_gmac")) {
|
|
|
|
debug("%s: switching GMAC to external clock\n", __func__);
|
|
|
|
rk_setreg(&cru->clksel_con[43], GMAC_MUX_SEL_EXTCLK);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2018-01-25 14:27:10 +00:00
|
|
|
static int __maybe_unused rk3368_clk_set_parent(struct clk *clk, struct clk *parent)
|
2018-01-13 06:07:04 +00:00
|
|
|
{
|
|
|
|
switch (clk->id) {
|
|
|
|
case SCLK_MAC:
|
|
|
|
return rk3368_gmac_set_parent(clk, parent);
|
|
|
|
}
|
|
|
|
|
|
|
|
debug("%s: unsupported clk %ld\n", __func__, clk->id);
|
|
|
|
return -ENOENT;
|
|
|
|
}
|
|
|
|
|
2017-05-15 09:49:56 +00:00
|
|
|
static struct clk_ops rk3368_clk_ops = {
|
|
|
|
.get_rate = rk3368_clk_get_rate,
|
|
|
|
.set_rate = rk3368_clk_set_rate,
|
2021-08-07 13:24:03 +00:00
|
|
|
#if CONFIG_IS_ENABLED(OF_REAL)
|
2018-01-13 06:07:04 +00:00
|
|
|
.set_parent = rk3368_clk_set_parent,
|
2018-01-25 14:27:10 +00:00
|
|
|
#endif
|
2017-05-15 09:49:56 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static int rk3368_clk_probe(struct udevice *dev)
|
|
|
|
{
|
2017-06-22 21:53:44 +00:00
|
|
|
struct rk3368_clk_priv __maybe_unused *priv = dev_get_priv(dev);
|
2017-06-22 21:51:37 +00:00
|
|
|
#if CONFIG_IS_ENABLED(OF_PLATDATA)
|
2020-12-03 23:55:20 +00:00
|
|
|
struct rk3368_clk_plat *plat = dev_get_plat(dev);
|
2017-05-15 09:49:56 +00:00
|
|
|
|
2017-08-29 20:15:50 +00:00
|
|
|
priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
|
2017-06-22 21:51:37 +00:00
|
|
|
#endif
|
2017-06-22 21:53:44 +00:00
|
|
|
#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
|
2017-05-15 09:49:56 +00:00
|
|
|
rkclk_init(priv->cru);
|
2017-06-22 21:53:44 +00:00
|
|
|
#endif
|
2017-05-15 09:49:56 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-12-03 23:55:21 +00:00
|
|
|
static int rk3368_clk_of_to_plat(struct udevice *dev)
|
2017-05-15 09:49:56 +00:00
|
|
|
{
|
2021-08-07 13:24:06 +00:00
|
|
|
if (CONFIG_IS_ENABLED(OF_REAL)) {
|
|
|
|
struct rk3368_clk_priv *priv = dev_get_priv(dev);
|
2017-05-15 09:49:56 +00:00
|
|
|
|
2021-08-07 13:24:06 +00:00
|
|
|
priv->cru = dev_read_addr_ptr(dev);
|
|
|
|
}
|
2017-05-15 09:49:56 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int rk3368_clk_bind(struct udevice *dev)
|
|
|
|
{
|
|
|
|
int ret;
|
2017-11-03 07:16:13 +00:00
|
|
|
struct udevice *sys_child;
|
|
|
|
struct sysreset_reg *priv;
|
2017-05-15 09:49:56 +00:00
|
|
|
|
|
|
|
/* The reset driver does not have a device node, so bind it here */
|
2017-11-03 07:16:13 +00:00
|
|
|
ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
|
|
|
|
&sys_child);
|
|
|
|
if (ret) {
|
|
|
|
debug("Warning: No sysreset driver: ret=%d\n", ret);
|
|
|
|
} else {
|
|
|
|
priv = malloc(sizeof(struct sysreset_reg));
|
|
|
|
priv->glb_srst_fst_value = offsetof(struct rk3368_cru,
|
|
|
|
glb_srst_fst_val);
|
|
|
|
priv->glb_srst_snd_value = offsetof(struct rk3368_cru,
|
|
|
|
glb_srst_snd_val);
|
2020-12-23 02:30:28 +00:00
|
|
|
dev_set_priv(sys_child, priv);
|
2017-11-03 07:16:13 +00:00
|
|
|
}
|
2017-05-15 09:49:56 +00:00
|
|
|
|
2019-11-08 23:06:30 +00:00
|
|
|
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
|
2017-12-19 10:22:38 +00:00
|
|
|
ret = offsetof(struct rk3368_cru, softrst_con[0]);
|
|
|
|
ret = rockchip_reset_bind(dev, ret, 15);
|
|
|
|
if (ret)
|
2023-04-11 07:17:56 +00:00
|
|
|
debug("Warning: software reset driver bind failed\n");
|
2017-12-19 10:22:38 +00:00
|
|
|
#endif
|
|
|
|
|
2017-05-15 09:49:56 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct udevice_id rk3368_clk_ids[] = {
|
|
|
|
{ .compatible = "rockchip,rk3368-cru" },
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
U_BOOT_DRIVER(rockchip_rk3368_cru) = {
|
|
|
|
.name = "rockchip_rk3368_cru",
|
|
|
|
.id = UCLASS_CLK,
|
|
|
|
.of_match = rk3368_clk_ids,
|
2020-12-03 23:55:17 +00:00
|
|
|
.priv_auto = sizeof(struct rk3368_clk_priv),
|
2017-06-22 21:51:37 +00:00
|
|
|
#if CONFIG_IS_ENABLED(OF_PLATDATA)
|
2020-12-03 23:55:18 +00:00
|
|
|
.plat_auto = sizeof(struct rk3368_clk_plat),
|
2017-06-22 21:51:37 +00:00
|
|
|
#endif
|
2020-12-03 23:55:21 +00:00
|
|
|
.of_to_plat = rk3368_clk_of_to_plat,
|
2017-05-15 09:49:56 +00:00
|
|
|
.ops = &rk3368_clk_ops,
|
|
|
|
.bind = rk3368_clk_bind,
|
|
|
|
.probe = rk3368_clk_probe,
|
|
|
|
};
|