2018-06-14 18:08:35 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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/*
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2020-04-19 13:58:30 +00:00
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* Common clock driver for Actions Semi SoCs.
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2018-06-14 18:08:35 +00:00
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*
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* Copyright (C) 2015 Actions Semi Co., Ltd.
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* Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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*/
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#include <common.h>
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#include <dm.h>
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2020-04-19 13:58:30 +00:00
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#include "clk_owl.h"
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2018-06-14 18:08:35 +00:00
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#include <asm/io.h>
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2020-04-19 13:58:30 +00:00
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#if defined(CONFIG_MACH_S900)
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#include <asm/arch-owl/regs_s900.h>
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2020-04-19 13:58:28 +00:00
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#include <dt-bindings/clock/actions,s900-cmu.h>
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2020-04-19 13:58:30 +00:00
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#elif defined(CONFIG_MACH_S700)
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#include <asm/arch-owl/regs_s700.h>
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#include <dt-bindings/clock/actions,s700-cmu.h>
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#endif
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2020-05-10 17:40:13 +00:00
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#include <linux/bitops.h>
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2020-05-10 17:40:11 +00:00
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#include <linux/delay.h>
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2018-06-14 18:08:35 +00:00
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2021-11-28 11:32:21 +00:00
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#define CMU_DEVCLKEN0_SD0 BIT(22)
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2018-06-14 18:08:35 +00:00
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void owl_clk_init(struct owl_clk_priv *priv)
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{
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u32 bus_clk = 0, core_pll, dev_pll;
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2020-04-19 13:58:30 +00:00
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#if defined(CONFIG_MACH_S900)
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2018-06-14 18:08:35 +00:00
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/* Enable ASSIST_PLL */
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setbits_le32(priv->base + CMU_ASSISTPLL, BIT(0));
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udelay(PLL_STABILITY_WAIT_US);
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2020-04-19 13:58:30 +00:00
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#endif
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2018-06-14 18:08:35 +00:00
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/* Source HOSC to DEV_CLK */
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clrbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
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/* Configure BUS_CLK */
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bus_clk |= (CMU_PDBGDIV_DIV | CMU_PERDIV_DIV | CMU_NOCDIV_DIV |
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CMU_DMMCLK_SRC | CMU_APBCLK_DIV | CMU_AHBCLK_DIV |
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CMU_NOCCLK_SRC | CMU_CORECLK_HOSC);
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writel(bus_clk, priv->base + CMU_BUSCLK);
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udelay(PLL_STABILITY_WAIT_US);
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/* Configure CORE_PLL */
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core_pll = readl(priv->base + CMU_COREPLL);
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core_pll |= (CMU_COREPLL_EN | CMU_COREPLL_HOSC_EN | CMU_COREPLL_OUT);
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writel(core_pll, priv->base + CMU_COREPLL);
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udelay(PLL_STABILITY_WAIT_US);
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/* Configure DEV_PLL */
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dev_pll = readl(priv->base + CMU_DEVPLL);
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dev_pll |= (CMU_DEVPLL_EN | CMU_DEVPLL_OUT);
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writel(dev_pll, priv->base + CMU_DEVPLL);
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udelay(PLL_STABILITY_WAIT_US);
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/* Source CORE_PLL for CORE_CLK */
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clrsetbits_le32(priv->base + CMU_BUSCLK, CMU_CORECLK_MASK,
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CMU_CORECLK_CPLL);
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/* Source DEV_PLL for DEV_CLK */
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setbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
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udelay(PLL_STABILITY_WAIT_US);
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}
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int owl_clk_enable(struct clk *clk)
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{
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struct owl_clk_priv *priv = dev_get_priv(clk->dev);
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2020-04-19 13:58:30 +00:00
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enum owl_soc model = dev_get_driver_data(clk->dev);
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2018-06-14 18:08:35 +00:00
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switch (clk->id) {
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2020-04-19 13:58:28 +00:00
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case CLK_UART5:
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2020-04-19 13:58:30 +00:00
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if (model != S900)
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return -EINVAL;
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/* Source HOSC for UART5 interface */
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clrbits_le32(priv->base + CMU_UART5CLK, CMU_UARTCLK_SRC_DEVPLL);
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/* Enable UART5 interface clock */
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setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);
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break;
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case CLK_UART3:
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if (model != S700)
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return -EINVAL;
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/* Source HOSC for UART3 interface */
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clrbits_le32(priv->base + CMU_UART3CLK, CMU_UARTCLK_SRC_DEVPLL);
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/* Enable UART3 interface clock */
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setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART3);
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2018-06-14 18:08:35 +00:00
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break;
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2020-05-09 14:25:09 +00:00
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case CLK_RMII_REF:
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case CLK_ETHERNET:
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setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_ETH);
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setbits_le32(priv->base + CMU_ETHERNETPLL, 5);
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break;
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2021-11-28 11:32:21 +00:00
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case CLK_SD0:
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setbits_le32(priv->base + CMU_DEVCLKEN0, CMU_DEVCLKEN0_SD0);
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break;
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2018-06-14 18:08:35 +00:00
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default:
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2020-04-19 13:58:30 +00:00
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return -EINVAL;
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2018-06-14 18:08:35 +00:00
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}
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return 0;
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}
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int owl_clk_disable(struct clk *clk)
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{
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struct owl_clk_priv *priv = dev_get_priv(clk->dev);
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2020-04-19 13:58:30 +00:00
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enum owl_soc model = dev_get_driver_data(clk->dev);
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2018-06-14 18:08:35 +00:00
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switch (clk->id) {
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2020-04-19 13:58:28 +00:00
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case CLK_UART5:
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2020-04-19 13:58:30 +00:00
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if (model != S900)
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return -EINVAL;
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/* Disable UART5 interface clock */
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clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);
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break;
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case CLK_UART3:
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if (model != S700)
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return -EINVAL;
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/* Disable UART3 interface clock */
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clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART3);
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2018-06-14 18:08:35 +00:00
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break;
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2020-05-09 14:25:09 +00:00
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case CLK_RMII_REF:
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case CLK_ETHERNET:
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clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_ETH);
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break;
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2021-11-28 11:32:21 +00:00
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case CLK_SD0:
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clrbits_le32(priv->base + CMU_DEVCLKEN0, CMU_DEVCLKEN0_SD0);
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break;
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2018-06-14 18:08:35 +00:00
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default:
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2020-04-19 13:58:30 +00:00
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return -EINVAL;
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2018-06-14 18:08:35 +00:00
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}
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return 0;
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}
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2021-11-28 11:32:21 +00:00
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static ulong get_sd_parent_rate(struct owl_clk_priv *priv, u32 dev_index)
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{
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ulong rate;
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u32 reg;
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reg = readl(priv->base + (CMU_SD0CLK + dev_index * 0x4));
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/* Clock output of DEV/NAND_PLL
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* Range: 48M ~ 756M
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* Frequency= PLLCLK * 6
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*/
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if (reg & 0x200)
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rate = readl(priv->base + CMU_NANDPLL) & 0x7f;
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else
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rate = readl(priv->base + CMU_DEVPLL) & 0x7f;
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rate *= 6000000;
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return rate;
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}
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static ulong owl_get_sd_clk_rate(struct owl_clk_priv *priv, int sd_index)
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{
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uint div, val;
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ulong parent_rate = get_sd_parent_rate(priv, sd_index);
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val = readl(priv->base + (CMU_SD0CLK + sd_index * 0x4));
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div = (val & 0x1f) + 1;
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return (parent_rate / div);
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}
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static ulong owl_set_sd_clk_rate(struct owl_clk_priv *priv, ulong rate,
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int sd_index)
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{
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uint div, val;
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ulong parent_rate = get_sd_parent_rate(priv, sd_index);
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if (rate == 0)
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return rate;
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div = (parent_rate / rate);
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val = readl(priv->base + (CMU_SD0CLK + sd_index * 0x4));
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/* Bits 4..0 is used to program div value and bit 8 to enable
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* divide by 128 circuit
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*/
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val &= ~0x11f;
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if (div >= 128) {
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div = div / 128;
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val |= 0x100; /* enable divide by 128 circuit */
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}
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val |= ((div - 1) & 0x1f);
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writel(val, priv->base + (CMU_SD0CLK + sd_index * 0x4));
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return owl_get_sd_clk_rate(priv, 0);
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}
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2021-11-28 11:32:20 +00:00
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static ulong owl_clk_get_rate(struct clk *clk)
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{
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2021-11-28 11:32:21 +00:00
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struct owl_clk_priv *priv = dev_get_priv(clk->dev);
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2021-11-28 11:32:20 +00:00
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ulong rate;
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switch (clk->id) {
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2021-11-28 11:32:21 +00:00
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case CLK_SD0:
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rate = owl_get_sd_clk_rate(priv, 0);
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break;
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2021-11-28 11:32:20 +00:00
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default:
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return -ENOENT;
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}
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return rate;
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}
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static ulong owl_clk_set_rate(struct clk *clk, ulong rate)
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{
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2021-11-28 11:32:21 +00:00
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struct owl_clk_priv *priv = dev_get_priv(clk->dev);
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2021-11-28 11:32:20 +00:00
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ulong new_rate;
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switch (clk->id) {
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2021-11-28 11:32:21 +00:00
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case CLK_SD0:
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new_rate = owl_set_sd_clk_rate(priv, rate, 0);
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break;
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2021-11-28 11:32:20 +00:00
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default:
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return -ENOENT;
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}
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return new_rate;
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}
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2018-06-14 18:08:35 +00:00
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static int owl_clk_probe(struct udevice *dev)
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{
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struct owl_clk_priv *priv = dev_get_priv(dev);
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priv->base = dev_read_addr(dev);
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if (priv->base == FDT_ADDR_T_NONE)
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return -EINVAL;
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/* setup necessary clocks */
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owl_clk_init(priv);
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return 0;
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}
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2020-04-19 13:58:30 +00:00
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static const struct clk_ops owl_clk_ops = {
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2018-06-14 18:08:35 +00:00
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.enable = owl_clk_enable,
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.disable = owl_clk_disable,
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2021-11-28 11:32:20 +00:00
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.get_rate = owl_clk_get_rate,
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.set_rate = owl_clk_set_rate,
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2018-06-14 18:08:35 +00:00
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};
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static const struct udevice_id owl_clk_ids[] = {
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2020-04-19 13:58:30 +00:00
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#if defined(CONFIG_MACH_S900)
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{ .compatible = "actions,s900-cmu", .data = S900 },
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#elif defined(CONFIG_MACH_S700)
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{ .compatible = "actions,s700-cmu", .data = S700 },
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#endif
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2018-06-14 18:08:35 +00:00
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{ }
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};
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U_BOOT_DRIVER(clk_owl) = {
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2020-04-19 13:58:30 +00:00
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.name = "clk_owl",
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2018-06-14 18:08:35 +00:00
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.id = UCLASS_CLK,
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.of_match = owl_clk_ids,
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.ops = &owl_clk_ops,
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2020-12-03 23:55:17 +00:00
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.priv_auto = sizeof(struct owl_clk_priv),
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2018-06-14 18:08:35 +00:00
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.probe = owl_clk_probe,
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};
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