2023-01-26 20:01:31 +00:00
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/* SPDX-License-Identifier: GPL-2.0+
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*
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2017-10-09 18:39:47 +00:00
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* Copyright (C) 2016 Renesas Electronics Corp.
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* Copyright (C) 2017 Cogent Embedded, Inc.
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*/
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#ifndef __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
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#define __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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/* r8a77970 CPG Core Clocks */
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#define R8A77970_CLK_Z2 0
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#define R8A77970_CLK_ZR 1
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#define R8A77970_CLK_ZTR 2
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#define R8A77970_CLK_ZTRD2 3
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#define R8A77970_CLK_ZT 4
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#define R8A77970_CLK_ZX 5
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#define R8A77970_CLK_S1D1 6
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#define R8A77970_CLK_S1D2 7
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#define R8A77970_CLK_S1D4 8
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#define R8A77970_CLK_S2D1 9
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#define R8A77970_CLK_S2D2 10
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#define R8A77970_CLK_S2D4 11
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#define R8A77970_CLK_LB 12
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#define R8A77970_CLK_CL 13
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#define R8A77970_CLK_ZB3 14
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#define R8A77970_CLK_ZB3D2 15
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#define R8A77970_CLK_DDR 16
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#define R8A77970_CLK_CR 17
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#define R8A77970_CLK_CRD2 18
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#define R8A77970_CLK_SD0H 19
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#define R8A77970_CLK_SD0 20
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#define R8A77970_CLK_RPC 21
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#define R8A77970_CLK_RPCD2 22
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#define R8A77970_CLK_MSO 23
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#define R8A77970_CLK_CANFD 24
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#define R8A77970_CLK_CSI0 25
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#define R8A77970_CLK_FRAY 26
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#define R8A77970_CLK_CP 27
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#define R8A77970_CLK_CPEX 28
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#define R8A77970_CLK_R 29
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#define R8A77970_CLK_OSC 30
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#endif /* __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ */
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