u-boot/arch/arm/dts/zynqmp-zcu102-rev1.1.dts

// SPDX-License-Identifier: GPL-2.0+
/*
 * dts file for Xilinx ZynqMP ZCU102 Rev1.1
 *
 * (C) Copyright 2016 - 2020, Xilinx, Inc.
 *
 * Michal Simek <michal.simek@amd.com>
 */

#include "zynqmp-zcu102-rev1.0.dts"

/ {
	model = "ZynqMP ZCU102 Rev1.1";
	compatible = "xlnx,zynqmp-zcu102-rev1.1", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
};
arm64: zynqmp Add support for zcu102 rev1.1 rev1.1 has different DDR sodimm module that's why it requires different DDR configuration. Signed-off-by: Michal Simek <michal.simek@xilinx.com> 2020-03-12 08:03:13 +00:00			`// SPDX-License-Identifier: GPL-2.0+`
			`/*`
			`* dts file for Xilinx ZynqMP ZCU102 Rev1.1`
			`*`
			`* (C) Copyright 2016 - 2020, Xilinx, Inc.`
			`*`
arm64: zynqmp: Switch to amd.com emails Update my and DPs email address to match current setup. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/aba5b19b9c5a95608829e86ad5cc4671c940f1bb.1688992543.git.michal.simek@amd.com 2023-07-10 12:35:49 +00:00			`* Michal Simek <michal.simek@amd.com>`
arm64: zynqmp Add support for zcu102 rev1.1 rev1.1 has different DDR sodimm module that's why it requires different DDR configuration. Signed-off-by: Michal Simek <michal.simek@xilinx.com> 2020-03-12 08:03:13 +00:00			`*/`

			`#include "zynqmp-zcu102-rev1.0.dts"`

			`/ {`
			`model = "ZynqMP ZCU102 Rev1.1";`
			`compatible = "xlnx,zynqmp-zcu102-rev1.1", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";`
			`};`