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u-boot/arch/arm/dts/k3-am65-mcu.dtsi

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arm: dts: k3: Sync dts from Linux Sync the k3-am654 specific dts files from Linux next with tag 20181019. This changes are in queue for Linux v4.20-rc1 Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-11-02 14:21:08 +00:00
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for AM6 SoC Family MCU Domain peripherals
*
arm: dts: k3-am65-mcu: Add MCU domain R5F DT nodes The AM65x SoCs has a single dual-core Arm Cortex-R5F processor subsystem/cluster (MCU_R5FSS0) within the MCU domain. This cluster can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. This subsystem has 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - ATCM and BTCM (further interleaved into two banks). There are some IP integration differences from standard Arm R5 clusters such as the absence of an ACP port, presence of an additional TI-specific Region Address Translater (RAT) module for translating 32-bit CPU addresses into larger system bus addresses etc. Add the DT node for the MCU domain R5F cluster/subsystem, the two R5 cores are added as child nodes to the main cluster/subsystem node. The cluster is configured to run in Split-mode by default, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-09-04 10:31:41 +00:00
* Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
arm: dts: k3: Sync dts from Linux Sync the k3-am654 specific dts files from Linux next with tag 20181019. This changes are in queue for Linux v4.20-rc1 Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-11-02 14:21:08 +00:00
*/
&cbass_mcu {
mcu_uart0: serial@40a00000 {
compatible = "ti,am654-uart";
reg = <0x00 0x40a00000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <96000000>;
current-speed = <115200>;
};
arm: dts: k3-am65: Add I2C nodes Add I2C DT nodes Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-06-04 23:08:14 +00:00
mcu_i2c0: i2c@40b00000 {
compatible = "ti,am654-i2c", "ti,omap4-i2c";
reg = <0x0 0x40b00000 0x0 0x100>;
interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 114 1>;
arm: dts: k3-am654: Update power-domains property for each node Update the power-domain-cells to 2 and add the permissions to each node. Mark the following nodes accessed by r5 as shared: - DDR node - main uart 0 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-06-07 13:54:47 +00:00
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
arm: dts: k3-am65: Add I2C nodes Add I2C DT nodes Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-06-04 23:08:14 +00:00
};
arm: dts: k3-am65-mcu: Add MCU domain R5F DT nodes The AM65x SoCs has a single dual-core Arm Cortex-R5F processor subsystem/cluster (MCU_R5FSS0) within the MCU domain. This cluster can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. This subsystem has 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - ATCM and BTCM (further interleaved into two banks). There are some IP integration differences from standard Arm R5 clusters such as the absence of an ACP port, presence of an additional TI-specific Region Address Translater (RAT) module for translating 32-bit CPU addresses into larger system bus addresses etc. Add the DT node for the MCU domain R5F cluster/subsystem, the two R5 cores are added as child nodes to the main cluster/subsystem node. The cluster is configured to run in Split-mode by default, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-09-04 10:31:41 +00:00
mcu_r5fss0: r5fss@41000000 {
compatible = "ti,am654-r5fss";
lockstep-mode = <0>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x41000000 0x00 0x41000000 0x20000>,
<0x41400000 0x00 0x41400000 0x20000>;
power-domains = <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>;
mcu_r5fss0_core0: r5f@41000000 {
compatible = "ti,am654-r5f";
reg = <0x41000000 0x00008000>,
<0x41010000 0x00008000>;
reg-names = "atcm", "btcm";
ti,sci = <&dmsc>;
ti,sci-dev-id = <159>;
ti,sci-proc-ids = <0x01 0xFF>;
resets = <&k3_reset 159 1>;
atcm-enable = <1>;
btcm-enable = <1>;
loczrama = <1>;
};
mcu_r5fss0_core1: r5f@41400000 {
compatible = "ti,am654-r5f";
reg = <0x41400000 0x00008000>,
<0x41410000 0x00008000>;
reg-names = "atcm", "btcm";
ti,sci = <&dmsc>;
ti,sci-dev-id = <245>;
ti,sci-proc-ids = <0x02 0xFF>;
resets = <&k3_reset 245 1>;
atcm-enable = <1>;
btcm-enable = <1>;
loczrama = <1>;
};
};
ARM: dts: k3-am65: Add OSPI DT nodes Add OSPI DT nodes to enable OSPI at U-Boot prompt and also to support OSPI boot. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-02-04 05:39:51 +00:00
fss: fss@47000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
ospi0: spi@47040000 {
compatible = "ti,am654-ospi", "cdns,qspi-nor";
reg = <0x0 0x47040000 0x0 0x100>,
<0x5 0x00000000 0x1 0x0000000>;
interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>;
cdns,fifo-depth = <256>;
cdns,fifo-width = <4>;
cdns,trigger-address = <0x0>;
clocks = <&k3_clks 248 0>;
assigned-clocks = <&k3_clks 248 0>;
assigned-clock-parents = <&k3_clks 248 2>;
assigned-clock-rates = <166666666>;
power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
};
ospi1: spi@47050000 {
compatible = "ti,am654-ospi", "cdns,qspi-nor";
reg = <0x0 0x47050000 0x0 0x100>,
<0x7 0x00000000 0x1 0x00000000>;
interrupts = <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
cdns,fifo-depth = <256>;
cdns,fifo-width = <4>;
cdns,trigger-address = <0x0>;
clocks = <&k3_clks 249 6>;
power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
};
};
arm: dts: k3-am65/j721e: Sync DMA DT bindings from Kernel DT Sync DT bindings from kernel DT and move them to out of -u-boot.dtsi files. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
2020-07-07 08:13:35 +00:00
mcu_navss {
compatible = "simple-mfd";
#address-cells = <2>;
#size-cells = <2>;
ranges;
dma-coherent;
dma-ranges;
ti,sci-dev-id = <119>;
mcu_ringacc: ringacc@2b800000 {
compatible = "ti,am654-navss-ringacc";
reg = <0x0 0x2b800000 0x0 0x400000>,
<0x0 0x2b000000 0x0 0x400000>,
<0x0 0x28590000 0x0 0x100>,
<0x0 0x2a500000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
ti,num-rings = <286>;
ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
ti,dma-ring-reset-quirk;
ti,sci = <&dmsc>;
ti,sci-dev-id = <195>;
};
mcu_udmap: dma-controller@285c0000 {
compatible = "ti,am654-navss-mcu-udmap";
reg = <0x0 0x285c0000 0x0 0x100>,
<0x0 0x2a800000 0x0 0x40000>,
<0x0 0x2aa00000 0x0 0x40000>;
reg-names = "gcfg", "rchanrt", "tchanrt";
#dma-cells = <1>;
ti,sci = <&dmsc>;
ti,sci-dev-id = <194>;
ti,ringacc = <&mcu_ringacc>;
ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
<0x2>; /* TX_CHAN */
ti,sci-rm-range-rchan = <0x3>, /* RX_HCHAN */
<0x4>; /* RX_CHAN */
ti,sci-rm-range-rflow = <0x5>; /* GP RFLOW */
};
};
arm: dts: k3: Sync dts from Linux Sync the k3-am654 specific dts files from Linux next with tag 20181019. This changes are in queue for Linux v4.20-rc1 Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-11-02 14:21:08 +00:00
};
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