2017-08-07 21:37:18 +00:00
|
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|
|
menuconfig NAND
|
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|
|
|
bool "NAND Device Support"
|
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|
|
if NAND
|
2014-10-03 10:21:03 +00:00
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|
2014-11-13 11:31:50 +00:00
|
|
|
config SYS_NAND_SELF_INIT
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bool
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|
help
|
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|
|
This option, if enabled, provides more flexible and linux-like
|
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|
|
|
NAND initialization process.
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|
2014-10-03 10:21:03 +00:00
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|
config NAND_DENALI
|
2017-12-06 04:51:50 +00:00
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bool
|
2014-11-13 11:31:50 +00:00
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|
|
select SYS_NAND_SELF_INIT
|
2017-07-29 01:31:42 +00:00
|
|
|
imply CMD_NAND
|
2014-10-03 10:21:03 +00:00
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|
2017-08-25 16:12:31 +00:00
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config NAND_DENALI_DT
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bool "Support Denali NAND controller as a DT device"
|
2017-12-06 04:51:50 +00:00
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|
|
select NAND_DENALI
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depends on OF_CONTROL && DM
|
2017-08-25 16:12:31 +00:00
|
|
|
help
|
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|
|
Enable the driver for NAND flash on platforms using a Denali NAND
|
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|
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controller as a DT device.
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2014-10-03 10:21:03 +00:00
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config NAND_DENALI_SPARE_AREA_SKIP_BYTES
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int "Number of bytes skipped in OOB area"
|
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|
depends on NAND_DENALI
|
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range 0 63
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|
help
|
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|
|
This option specifies the number of bytes to skip from the beginning
|
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|
|
of OOB area before last ECC sector data starts. This is potentially
|
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|
used to preserve the bad block marker in the OOB area.
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|
2017-10-16 19:08:26 +00:00
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|
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config NAND_OMAP_GPMC
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bool "Support OMAP GPMC NAND controller"
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|
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depends on ARCH_OMAP2PLUS
|
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help
|
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|
Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
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|
GPMC controller is used for parallel NAND flash devices, and can
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|
do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
|
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and BCH16 ECC algorithms.
|
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|
config NAND_OMAP_GPMC_PREFETCH
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bool "Enable GPMC Prefetch"
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|
|
depends on NAND_OMAP_GPMC
|
2017-10-20 20:55:51 +00:00
|
|
|
default y
|
2017-10-16 19:08:26 +00:00
|
|
|
help
|
|
|
|
|
On OMAP platforms that use the GPMC controller
|
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|
|
(CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
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|
uses the prefetch mode to speed up read operations.
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|
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config NAND_OMAP_ELM
|
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|
|
bool "Enable ELM driver for OMAPxx and AMxx platforms."
|
|
|
|
|
depends on NAND_OMAP_GPMC && !OMAP34XX
|
|
|
|
|
help
|
|
|
|
|
ELM controller is used for ECC error detection (not ECC calculation)
|
|
|
|
|
of BCH4, BCH8 and BCH16 ECC algorithms.
|
|
|
|
|
Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
|
|
|
|
|
thus such SoC platforms need to depend on software library for ECC error
|
|
|
|
|
detection. However ECC calculation on such plaforms would still be
|
|
|
|
|
done by GPMC controller.
|
|
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|
|
|
2015-05-08 17:07:11 +00:00
|
|
|
config NAND_VF610_NFC
|
2017-06-14 03:49:40 +00:00
|
|
|
bool "Support for Freescale NFC for VF610"
|
2015-05-08 17:07:11 +00:00
|
|
|
select SYS_NAND_SELF_INIT
|
2017-07-29 01:31:42 +00:00
|
|
|
imply CMD_NAND
|
2015-05-08 17:07:11 +00:00
|
|
|
help
|
|
|
|
|
Enables support for NAND Flash Controller on some Freescale
|
2017-06-14 03:49:40 +00:00
|
|
|
processors like the VF610, MCF54418 or Kinetis K70.
|
2015-05-08 17:07:11 +00:00
|
|
|
The driver supports a maximum 2k page size. The driver
|
|
|
|
|
currently does not support hardware ECC.
|
|
|
|
|
|
2015-05-08 17:07:12 +00:00
|
|
|
choice
|
|
|
|
|
prompt "Hardware ECC strength"
|
|
|
|
|
depends on NAND_VF610_NFC
|
|
|
|
|
default SYS_NAND_VF610_NFC_45_ECC_BYTES
|
|
|
|
|
help
|
|
|
|
|
Select the ECC strength used in the hardware BCH ECC block.
|
|
|
|
|
|
|
|
|
|
config SYS_NAND_VF610_NFC_45_ECC_BYTES
|
|
|
|
|
bool "24-error correction (45 ECC bytes)"
|
|
|
|
|
|
|
|
|
|
config SYS_NAND_VF610_NFC_60_ECC_BYTES
|
|
|
|
|
bool "32-error correction (60 ECC bytes)"
|
|
|
|
|
|
|
|
|
|
endchoice
|
|
|
|
|
|
2015-07-23 08:26:16 +00:00
|
|
|
config NAND_PXA3XX
|
|
|
|
|
bool "Support for NAND on PXA3xx and Armada 370/XP/38x"
|
|
|
|
|
select SYS_NAND_SELF_INIT
|
2017-07-29 01:31:42 +00:00
|
|
|
imply CMD_NAND
|
2015-07-23 08:26:16 +00:00
|
|
|
help
|
|
|
|
|
This enables the driver for the NAND flash device found on
|
|
|
|
|
PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
|
|
|
|
|
|
2015-08-16 12:48:22 +00:00
|
|
|
config NAND_SUNXI
|
2016-06-15 19:09:23 +00:00
|
|
|
bool "Support for NAND on Allwinner SoCs"
|
2015-08-16 12:48:22 +00:00
|
|
|
depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
|
|
|
|
|
select SYS_NAND_SELF_INIT
|
2017-02-27 17:22:08 +00:00
|
|
|
select SYS_NAND_U_BOOT_LOCATIONS
|
2017-07-29 01:31:42 +00:00
|
|
|
imply CMD_NAND
|
2015-08-16 12:48:22 +00:00
|
|
|
---help---
|
2016-06-15 19:09:23 +00:00
|
|
|
Enable support for NAND. This option enables the standard and
|
|
|
|
|
SPL drivers.
|
|
|
|
|
The SPL driver only supports reading from the NAND using DMA
|
|
|
|
|
transfers.
|
2015-08-16 12:48:22 +00:00
|
|
|
|
2017-02-27 17:22:12 +00:00
|
|
|
if NAND_SUNXI
|
|
|
|
|
|
|
|
|
|
config NAND_SUNXI_SPL_ECC_STRENGTH
|
|
|
|
|
int "Allwinner NAND SPL ECC Strength"
|
|
|
|
|
default 64
|
|
|
|
|
|
|
|
|
|
config NAND_SUNXI_SPL_ECC_SIZE
|
|
|
|
|
int "Allwinner NAND SPL ECC Step Size"
|
|
|
|
|
default 1024
|
|
|
|
|
|
|
|
|
|
config NAND_SUNXI_SPL_USABLE_PAGE_SIZE
|
|
|
|
|
int "Allwinner NAND SPL Usable Page Size"
|
|
|
|
|
default 1024
|
|
|
|
|
|
|
|
|
|
endif
|
|
|
|
|
|
2015-11-17 09:00:09 +00:00
|
|
|
config NAND_ARASAN
|
|
|
|
|
bool "Configure Arasan Nand"
|
2018-01-15 15:48:12 +00:00
|
|
|
select SYS_NAND_SELF_INIT
|
2017-07-29 01:31:42 +00:00
|
|
|
imply CMD_NAND
|
2015-11-17 09:00:09 +00:00
|
|
|
help
|
|
|
|
|
This enables Nand driver support for Arasan nand flash
|
|
|
|
|
controller. This uses the hardware ECC for read and
|
|
|
|
|
write operations.
|
|
|
|
|
|
2017-10-16 19:08:26 +00:00
|
|
|
config NAND_MXC
|
|
|
|
|
bool "MXC NAND support"
|
|
|
|
|
depends on CPU_ARM926EJS || CPU_ARM1136 || MX5
|
|
|
|
|
imply CMD_NAND
|
|
|
|
|
help
|
|
|
|
|
This enables the NAND driver for the NAND flash controller on the
|
|
|
|
|
i.MX27 / i.MX31 / i.MX5 rocessors.
|
|
|
|
|
|
2016-10-08 12:30:25 +00:00
|
|
|
config NAND_MXS
|
|
|
|
|
bool "MXS NAND support"
|
2018-02-06 08:44:37 +00:00
|
|
|
depends on MX23 || MX28 || MX6 || MX7
|
2017-07-29 01:31:42 +00:00
|
|
|
imply CMD_NAND
|
2016-10-08 12:30:25 +00:00
|
|
|
help
|
|
|
|
|
This enables NAND driver for the NAND flash controller on the
|
|
|
|
|
MXS processors.
|
|
|
|
|
|
2016-09-27 05:25:46 +00:00
|
|
|
config NAND_ZYNQ
|
|
|
|
|
bool "Support for Zynq Nand controller"
|
|
|
|
|
select SYS_NAND_SELF_INIT
|
2017-07-29 01:31:42 +00:00
|
|
|
imply CMD_NAND
|
2016-09-27 05:25:46 +00:00
|
|
|
help
|
|
|
|
|
This enables Nand driver support for Nand flash controller
|
|
|
|
|
found on Zynq SoC.
|
|
|
|
|
|
2017-11-06 08:34:46 +00:00
|
|
|
config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
|
|
|
|
|
bool "Enable use of 1st stage bootloader timing for NAND"
|
|
|
|
|
depends on NAND_ZYNQ
|
|
|
|
|
help
|
|
|
|
|
This flag prevent U-boot reconfigure NAND flash controller and reuse
|
|
|
|
|
the NAND timing from 1st stage bootloader.
|
|
|
|
|
|
2015-05-08 17:07:11 +00:00
|
|
|
comment "Generic NAND options"
|
|
|
|
|
|
|
|
|
|
# Enhance depends when converting drivers to Kconfig which use this config
|
|
|
|
|
# option (mxc_nand, ndfc, omap_gpmc).
|
|
|
|
|
config SYS_NAND_BUSWIDTH_16BIT
|
|
|
|
|
bool "Use 16-bit NAND interface"
|
2017-10-16 19:08:26 +00:00
|
|
|
depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI
|
2015-05-08 17:07:11 +00:00
|
|
|
help
|
|
|
|
|
Indicates that NAND device has 16-bit wide data-bus. In absence of this
|
|
|
|
|
config, bus-width of NAND device is assumed to be either 8-bit and later
|
|
|
|
|
determined by reading ONFI params.
|
|
|
|
|
Above config is useful when NAND device's bus-width information cannot
|
|
|
|
|
be determined from on-chip ONFI params, like in following scenarios:
|
|
|
|
|
- SPL boot does not support reading of ONFI parameters. This is done to
|
|
|
|
|
keep SPL code foot-print small.
|
|
|
|
|
- In current U-Boot flow using nand_init(), driver initialization
|
|
|
|
|
happens in board_nand_init() which is called before any device probe
|
|
|
|
|
(nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are
|
|
|
|
|
not available while configuring controller. So a static CONFIG_NAND_xx
|
|
|
|
|
is needed to know the device's bus-width in advance.
|
|
|
|
|
|
2016-06-06 08:16:57 +00:00
|
|
|
if SPL
|
|
|
|
|
|
|
|
|
|
config SYS_NAND_U_BOOT_LOCATIONS
|
|
|
|
|
bool "Define U-boot binaries locations in NAND"
|
|
|
|
|
help
|
|
|
|
|
Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig.
|
|
|
|
|
This option should not be enabled when compiling U-boot for boards
|
|
|
|
|
defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h
|
|
|
|
|
file.
|
|
|
|
|
|
2015-08-21 19:49:51 +00:00
|
|
|
config SYS_NAND_U_BOOT_OFFS
|
|
|
|
|
hex "Location in NAND to read U-Boot from"
|
mtd: sunxi: Change U-Boot offset
The default U-Boot offset for the Allwinner SoCs was set to 32kB.
This was probably to try to maintain some compatibility with the current
image that we build for the MMC where the U-Boot binary is also located at
a 32kB offset.
However, this causes a number of issues. The first one is that it prevents
us from using a backup SPL entirely, which is troublesome in case where the
first would be corrupt (especially on MLC which have a higher number of
bitflips).
We also cannot use the original MMC image on the NAND, because we need to
prepare the SPL image to include the ECCs and randomizer settings, which
reduces the interest of setting it at that particular offset.
It also prevents us from upgrading and flashing the U-Boot and SPLs
independantly, since it's very likely that it will fall in the same erase
block.
Since that default wasn't used by any board, change it for 8MB, which will
be in an erase block of its own, all the erase blocks being multiple of
two. The highest erase block size we encountered is 4MB, which means that
in this particular setup, the first and second erase blocks will be for the
SPL and its backup, and the third for U-Boot.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-02-27 17:22:09 +00:00
|
|
|
default 0x800000 if NAND_SUNXI
|
2016-06-06 08:16:57 +00:00
|
|
|
depends on SYS_NAND_U_BOOT_LOCATIONS
|
2015-08-21 19:49:51 +00:00
|
|
|
help
|
|
|
|
|
Set the offset from the start of the nand where u-boot should be
|
|
|
|
|
loaded from.
|
|
|
|
|
|
2016-06-06 08:16:58 +00:00
|
|
|
config SYS_NAND_U_BOOT_OFFS_REDUND
|
|
|
|
|
hex "Location in NAND to read U-Boot from"
|
|
|
|
|
default SYS_NAND_U_BOOT_OFFS
|
|
|
|
|
depends on SYS_NAND_U_BOOT_LOCATIONS
|
|
|
|
|
help
|
|
|
|
|
Set the offset from the start of the nand where the redundant u-boot
|
|
|
|
|
should be loaded from.
|
|
|
|
|
|
2017-10-16 19:08:26 +00:00
|
|
|
config SPL_NAND_AM33XX_BCH
|
|
|
|
|
bool "Enables SPL-NAND driver which supports ELM based"
|
|
|
|
|
depends on NAND_OMAP_GPMC && !OMAP34XX
|
|
|
|
|
default y
|
|
|
|
|
help
|
|
|
|
|
Hardware ECC correction. This is useful for platforms which have ELM
|
|
|
|
|
hardware engine and use NAND boot mode.
|
|
|
|
|
Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
|
|
|
|
|
so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
|
|
|
|
|
SPL-NAND driver with software ECC correction support.
|
|
|
|
|
|
2014-10-03 10:21:04 +00:00
|
|
|
config SPL_NAND_DENALI
|
|
|
|
|
bool "Support Denali NAND controller for SPL"
|
|
|
|
|
help
|
|
|
|
|
This is a small implementation of the Denali NAND controller
|
|
|
|
|
for use on SPL.
|
|
|
|
|
|
2017-10-16 19:08:26 +00:00
|
|
|
config SPL_NAND_SIMPLE
|
|
|
|
|
bool "Use simple SPL NAND driver"
|
|
|
|
|
depends on !SPL_NAND_AM33XX_BCH
|
|
|
|
|
help
|
|
|
|
|
Support for NAND boot using simple NAND drivers that
|
|
|
|
|
expose the cmd_ctrl() interface.
|
2014-10-03 10:21:04 +00:00
|
|
|
endif
|
|
|
|
|
|
2017-08-07 21:37:18 +00:00
|
|
|
endif # if NAND
|
