u-boot/arch/x86/cpu/coreboot/pci.c

/*
 * Copyright (c) 2011 The Chromium OS Authors.
 * (C) Copyright 2008,2009
 * Graeme Russ, <graeme.russ@gmail.com>
 *
 * (C) Copyright 2002
 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <dm.h>
#include <pci.h>

static const struct udevice_id generic_pch_ids[] = {
	{ .compatible = "intel,pch7" },
	{ .compatible = "intel,pch9" },
	{ }
};

U_BOOT_DRIVER(generic_pch_drv) = {
	.name		= "pch",
	.id		= UCLASS_PCH,
	.of_match	= generic_pch_ids,
};
x86: Initial commit for running as a coreboot payload Add a target for running u-boot as a coreboot payload in boards.cfg, a board, CPU and a config. This is a skeleton implementation which always reports the size of memory as 64 MB. Signed-off-by: Gabe Black <gabeblack@chromium.org> 2011-11-29 18:05:07 +00:00			`/*`
			`* Copyright (c) 2011 The Chromium OS Authors.`
			`* (C) Copyright 2008,2009`
			`* Graeme Russ, <graeme.russ@gmail.com>`
			`*`
			`* (C) Copyright 2002`
			`* Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>`
			`*`
Coding Style cleanup: remove trailing white space Signed-off-by: Wolfgang Denk <wd@denx.de> 2013-10-07 11:07:26 +00:00			`* SPDX-License-Identifier: GPL-2.0+`
x86: Initial commit for running as a coreboot payload Add a target for running u-boot as a coreboot payload in boards.cfg, a board, CPU and a config. This is a skeleton implementation which always reports the size of memory as 64 MB. Signed-off-by: Gabe Black <gabeblack@chromium.org> 2011-11-29 18:05:07 +00:00			`*/`

x86: coreboot: Tell u-boot about PCI bus 0 when initializing U-boot needs a host controller or "hose" to interact with the PCI busses behind them. This change installs a host controller during initialization of the coreboot "board" which implements some of X86's basic PCI semantics. This relies on some existing generic code, but also duplicates a little bit of code from the sc520 implementation. Ideally we'd eliminate that duplication at some point. It looks like in order to scan buses beyond bus 0, we'll need to tell u-boot's generic PCI configuration code what to do if it encounters a bridge, specifically to scan the bus on the other side of it. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Graeme Russ <graeme.russ@gmail.com> 2012-10-10 13:12:57 +00:00			`#include <common.h>`
dm: x86: pci: Convert coreboot to use driver model for pci Move coreboot-x86 over to driver model for PCI. Signed-off-by: Simon Glass <sjg@chromium.org> 2015-03-05 19:25:32 +00:00			`#include <dm.h>`
x86: coreboot: Tell u-boot about PCI bus 0 when initializing U-boot needs a host controller or "hose" to interact with the PCI busses behind them. This change installs a host controller during initialization of the coreboot "board" which implements some of X86's basic PCI semantics. This relies on some existing generic code, but also duplicates a little bit of code from the sc520 implementation. Ideally we'd eliminate that duplication at some point. It looks like in order to scan buses beyond bus 0, we'll need to tell u-boot's generic PCI configuration code what to do if it encounters a bridge, specifically to scan the bus on the other side of it. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Graeme Russ <graeme.russ@gmail.com> 2012-10-10 13:12:57 +00:00			`#include <pci.h>`
x86: link: Add PCH driver to support SPI Flash U-Boot on coreboot does not have a driver for the PCH so cannot see the SPI peripheral now that it has moved inside the PCH. Add a simple driver so that SPI flash works again. Signed-off-by: Simon Glass <sjg@chromium.org> 2015-04-20 13:07:03 +00:00
			`static const struct udevice_id generic_pch_ids[] = {`
dm: x86: spi: Convert ICH SPI driver to driver model PCI API At present this SPI driver works by searching the PCI buses for its peripheral. It also uses the legacy PCI API. In addition the driver has code to determine the type of Intel PCH that is used (version 7 or version 9). Now that we have proper PCH drivers we can use those to obtain the information we need. While the device tree has a node for the SPI peripheral it is not in the right place. It should be on the PCI bus as a sub-peripheral of the LPC device. Update the device tree files to show the SPI controller within the PCH, so that PCI access works as expected. This patch includes Bin's fix-up patch from here: https://patchwork.ozlabs.org/patch/569478/ Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> 2016-01-19 03:19:21 +00:00			`{ .compatible = "intel,pch7" },`
			`{ .compatible = "intel,pch9" },`
x86: link: Add PCH driver to support SPI Flash U-Boot on coreboot does not have a driver for the PCH so cannot see the SPI peripheral now that it has moved inside the PCH. Add a simple driver so that SPI flash works again. Signed-off-by: Simon Glass <sjg@chromium.org> 2015-04-20 13:07:03 +00:00			`{ }`
			`};`

			`U_BOOT_DRIVER(generic_pch_drv) = {`
			`.name = "pch",`
			`.id = UCLASS_PCH,`
			`.of_match = generic_pch_ids,`
			`};`