2023-06-30 07:29:04 +00:00
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// SPDX-License-Identifier: GPL-2.0
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#include <dt-bindings/input/input.h>
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#include "tegra30.dtsi"
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/ {
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chosen {
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stdout-path = &uarta;
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};
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aliases {
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i2c0 = &pwr_i2c;
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mmc0 = &sdmmc4; /* eMMC */
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rtc0 = &pmic;
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rtc1 = "/rtc@7000e000";
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usb0 = &usb1;
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};
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memory {
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device_type = "memory";
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reg = <0x80000000 0x40000000>;
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};
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host1x@50000000 {
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dc@54200000 {
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nvidia,180-rotation;
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rgb {
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status = "okay";
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nvidia,panel = <&panel>;
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};
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};
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};
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gpio@6000d000 {
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volume-buttons-hog {
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gpio-hog;
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gpios = <TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>,
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<TEGRA_GPIO(Q, 0) GPIO_ACTIVE_HIGH>;
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output-low;
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};
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};
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2023-11-27 16:16:50 +00:00
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pinmux@70000868 {
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pinctrl-names = "default";
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pinctrl-0 = <&state_default>;
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state_default: pinmux {
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clk_32k_out_pa0 {
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nvidia,pins = "clk_32k_out_pa0";
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nvidia,function = "blink";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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uart3_cts_n_pa1 {
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nvidia,pins = "uart3_cts_n_pa1",
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"uart3_rxd_pw7";
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nvidia,function = "uartc";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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dap2_fs_pa2 {
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nvidia,pins = "dap2_fs_pa2",
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"dap2_sclk_pa3",
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"dap2_din_pa4",
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"dap2_dout_pa5";
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nvidia,function = "i2s1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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sdmmc3_clk_pa6 {
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nvidia,pins = "sdmmc3_clk_pa6";
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nvidia,function = "sdmmc3";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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sdmmc3_cmd_pa7 {
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nvidia,pins = "sdmmc3_cmd_pa7",
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"sdmmc3_dat3_pb4",
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"sdmmc3_dat2_pb5",
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"sdmmc3_dat1_pb6",
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"sdmmc3_dat0_pb7",
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"sdmmc3_dat4_pd1",
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"sdmmc3_dat6_pd3",
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"sdmmc3_dat7_pd4";
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nvidia,function = "sdmmc3";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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gmi_a17_pb0 {
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nvidia,pins = "gmi_a17_pb0",
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"gmi_a18_pb1";
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nvidia,function = "uartd";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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lcd_pwr0_pb2 {
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nvidia,pins = "lcd_pwr0_pb2",
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"lcd_pwr1_pc1",
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"lcd_m1_pw1";
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nvidia,function = "displaya";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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lcd_pclk_pb3 {
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nvidia,pins = "lcd_pclk_pb3",
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"lcd_d0_pe0",
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"lcd_d1_pe1",
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"lcd_d2_pe2",
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"lcd_d3_pe3",
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"lcd_d4_pe4",
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"lcd_d5_pe5",
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"lcd_d6_pe6",
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"lcd_d7_pe7",
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"lcd_d8_pf0",
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"lcd_d9_pf1",
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"lcd_d10_pf2",
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"lcd_d11_pf3",
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"lcd_d12_pf4",
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"lcd_d13_pf5",
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"lcd_d14_pf6",
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"lcd_d15_pf7",
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"lcd_de_pj1",
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"lcd_hsync_pj3",
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"lcd_vsync_pj4",
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"lcd_d16_pm0",
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"lcd_d17_pm1",
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"lcd_d18_pm2",
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"lcd_d19_pm3",
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"lcd_d20_pm4",
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"lcd_d21_pm5",
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"lcd_d22_pm6",
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"lcd_d23_pm7",
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"lcd_cs0_n_pn4",
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"lcd_sdout_pn5",
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"lcd_dc0_pn6",
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"lcd_cs1_n_pw0",
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"lcd_sdin_pz2",
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"lcd_sck_pz4";
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nvidia,function = "displaya";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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uart3_rts_n_pc0 {
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nvidia,pins = "uart3_rts_n_pc0",
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"uart3_txd_pw6";
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nvidia,function = "uartc";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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uart2_txd_pc2 {
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nvidia,pins = "uart2_txd_pc2",
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"uart2_rts_n_pj6";
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nvidia,function = "uartb";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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uart2_rxd_pc3 {
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nvidia,pins = "uart2_rxd_pc3",
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"uart2_cts_n_pj5";
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nvidia,function = "uartb";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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gen1_i2c_scl_pc4 {
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nvidia,pins = "gen1_i2c_scl_pc4",
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"gen1_i2c_sda_pc5";
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nvidia,function = "i2c1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,open-drain = <TEGRA_PIN_ENABLE>;
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};
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gmi_wp_n_pc7 {
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nvidia,pins = "gmi_wp_n_pc7",
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"gmi_wait_pi7",
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"gmi_cs4_n_pk2",
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"gmi_cs3_n_pk4";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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gmi_ad12_ph4 {
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nvidia,pins = "gmi_ad12_ph4",
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"gmi_cs0_n_pj0",
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"gmi_cs1_n_pj2",
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"gmi_cs2_n_pk3";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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sdmmc3_dat5_pd0 {
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nvidia,pins = "sdmmc3_dat5_pd0";
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nvidia,function = "sdmmc3";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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gmi_ad0_pg0 {
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nvidia,pins = "gmi_ad0_pg0",
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"gmi_ad1_pg1",
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"gmi_ad14_ph6",
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"pu1";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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gmi_ad2_pg2 {
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nvidia,pins = "gmi_ad2_pg2",
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"gmi_ad3_pg3",
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"gmi_ad6_pg6",
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"gmi_ad7_pg7";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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gmi_ad4_pg4 {
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nvidia,pins = "gmi_ad4_pg4",
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"gmi_ad5_pg5";
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nvidia,function = "nand";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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gmi_ad8_ph0 {
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nvidia,pins = "gmi_ad8_ph0";
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nvidia,function = "pwm0";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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gmi_ad9_ph1 {
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nvidia,pins = "gmi_ad9_ph1";
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nvidia,function = "rsvd4";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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gmi_ad10_ph2 {
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nvidia,pins = "gmi_ad10_ph2";
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nvidia,function = "pwm2";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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gmi_ad11_ph3 {
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nvidia,pins = "gmi_ad11_ph3";
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nvidia,function = "pwm3";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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gmi_ad13_ph5 {
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nvidia,pins = "gmi_ad13_ph5",
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"gmi_wr_n_pi0",
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"gmi_oe_n_pi1",
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"gmi_adv_n_pk0";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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gmi_ad15_ph7 {
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nvidia,pins = "gmi_ad15_ph7";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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gmi_dqs_pi2 {
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nvidia,pins = "gmi_dqs_pi2",
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"pu2",
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"pv1";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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gmi_rst_n_pi4 {
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nvidia,pins = "gmi_rst_n_pi4";
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nvidia,function = "nand";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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gmi_iordy_pi5 {
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nvidia,pins = "gmi_iordy_pi5";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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gmi_cs7_n_pi6 {
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nvidia,pins = "gmi_cs7_n_pi6",
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"gmi_clk_pk1";
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nvidia,function = "nand";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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gmi_a16_pj7 {
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nvidia,pins = "gmi_a16_pj7",
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"gmi_a19_pk7";
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nvidia,function = "uartd";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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spdif_out_pk5 {
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nvidia,pins = "spdif_out_pk5";
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nvidia,function = "spdif";
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|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
spdif_in_pk6 {
|
|
|
|
nvidia,pins = "spdif_in_pk6";
|
|
|
|
nvidia,function = "spdif";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
dap1_fs_pn0 {
|
|
|
|
nvidia,pins = "dap1_fs_pn0",
|
|
|
|
"dap1_din_pn1",
|
|
|
|
"dap1_dout_pn2",
|
|
|
|
"dap1_sclk_pn3";
|
|
|
|
nvidia,function = "i2s0";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
hdmi_int_pn7 {
|
|
|
|
nvidia,pins = "hdmi_int_pn7";
|
|
|
|
nvidia,function = "hdmi";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
ulpi_data7_po0 {
|
|
|
|
nvidia,pins = "ulpi_data7_po0";
|
|
|
|
nvidia,function = "uarta";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
ulpi_data3_po4 {
|
|
|
|
nvidia,pins = "ulpi_data3_po4";
|
|
|
|
nvidia,function = "ulpi";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
dap3_fs_pp0 {
|
|
|
|
nvidia,pins = "dap3_fs_pp0";
|
|
|
|
nvidia,function = "i2s2";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
dap4_fs_pp4 {
|
|
|
|
nvidia,pins = "dap4_fs_pp4",
|
|
|
|
"dap4_din_pp5",
|
|
|
|
"dap4_dout_pp6",
|
|
|
|
"dap4_sclk_pp7";
|
|
|
|
nvidia,function = "i2s3";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
kb_col0_pq0 {
|
|
|
|
nvidia,pins = "kb_col0_pq0",
|
|
|
|
"kb_col1_pq1",
|
|
|
|
"kb_row1_pr1";
|
|
|
|
nvidia,function = "kbc";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
kb_col2_pq2 {
|
|
|
|
nvidia,pins = "kb_col2_pq2",
|
|
|
|
"kb_col3_pq3";
|
|
|
|
nvidia,function = "rsvd4";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
kb_col4_pq4 {
|
|
|
|
nvidia,pins = "kb_col4_pq4",
|
|
|
|
"kb_col5_pq5",
|
|
|
|
"kb_col7_pq7",
|
|
|
|
"kb_row2_pr2",
|
|
|
|
"kb_row4_pr4",
|
|
|
|
"kb_row5_pr5",
|
|
|
|
"kb_row14_ps6";
|
|
|
|
nvidia,function = "kbc";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
kb_row0_pr0 {
|
|
|
|
nvidia,pins = "kb_row0_pr0";
|
|
|
|
nvidia,function = "rsvd4";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
kb_row6_pr6 {
|
|
|
|
nvidia,pins = "kb_row6_pr6",
|
|
|
|
"kb_row8_ps0",
|
|
|
|
"kb_row9_ps1",
|
|
|
|
"kb_row10_ps2";
|
|
|
|
nvidia,function = "kbc";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
kb_row11_ps3 {
|
|
|
|
nvidia,pins = "kb_row11_ps3",
|
|
|
|
"kb_row12_ps4";
|
|
|
|
nvidia,function = "kbc";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
gen2_i2c_scl_pt5 {
|
|
|
|
nvidia,pins = "gen2_i2c_scl_pt5",
|
|
|
|
"gen2_i2c_sda_pt6";
|
|
|
|
nvidia,function = "i2c2";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
sdmmc4_cmd_pt7 {
|
|
|
|
nvidia,pins = "sdmmc4_cmd_pt7",
|
|
|
|
"sdmmc4_dat0_paa0",
|
|
|
|
"sdmmc4_dat1_paa1",
|
|
|
|
"sdmmc4_dat2_paa2",
|
|
|
|
"sdmmc4_dat3_paa3",
|
|
|
|
"sdmmc4_dat4_paa4",
|
|
|
|
"sdmmc4_dat5_paa5",
|
|
|
|
"sdmmc4_dat6_paa6",
|
|
|
|
"sdmmc4_dat7_paa7";
|
|
|
|
nvidia,function = "sdmmc4";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
pu0 {
|
|
|
|
nvidia,pins = "pu0",
|
|
|
|
"pu6";
|
|
|
|
nvidia,function = "rsvd4";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
jtag_rtck_pu7 {
|
|
|
|
nvidia,pins = "jtag_rtck_pu7";
|
|
|
|
nvidia,function = "rtck";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
pv0 {
|
|
|
|
nvidia,pins = "pv0";
|
|
|
|
nvidia,function = "rsvd1";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
ddc_scl_pv4 {
|
|
|
|
nvidia,pins = "ddc_scl_pv4",
|
|
|
|
"ddc_sda_pv5";
|
|
|
|
nvidia,function = "i2c4";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
crt_hsync_pv6 {
|
|
|
|
nvidia,pins = "crt_hsync_pv6",
|
|
|
|
"crt_vsync_pv7";
|
|
|
|
nvidia,function = "crt";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
spi2_cs1_n_pw2 {
|
|
|
|
nvidia,pins = "spi2_cs1_n_pw2",
|
|
|
|
"spi2_miso_px1",
|
|
|
|
"spi2_sck_px2";
|
|
|
|
nvidia,function = "spi2";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
clk1_out_pw4 {
|
|
|
|
nvidia,pins = "clk1_out_pw4";
|
|
|
|
nvidia,function = "extperiph1";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
clk2_out_pw5 {
|
|
|
|
nvidia,pins = "clk2_out_pw5";
|
|
|
|
nvidia,function = "extperiph2";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
spi2_cs0_n_px3 {
|
|
|
|
nvidia,pins = "spi2_cs0_n_px3";
|
|
|
|
nvidia,function = "spi6";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
spi1_mosi_px4 {
|
|
|
|
nvidia,pins = "spi1_mosi_px4",
|
|
|
|
"spi1_cs0_n_px6";
|
|
|
|
nvidia,function = "spi1";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
ulpi_clk_py0 {
|
|
|
|
nvidia,pins = "ulpi_clk_py0",
|
|
|
|
"ulpi_dir_py1";
|
|
|
|
nvidia,function = "ulpi";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
sdmmc1_dat3_py4 {
|
|
|
|
nvidia,pins = "sdmmc1_dat3_py4",
|
|
|
|
"sdmmc1_dat2_py5",
|
|
|
|
"sdmmc1_dat1_py6",
|
|
|
|
"sdmmc1_dat0_py7",
|
|
|
|
"sdmmc1_cmd_pz1";
|
|
|
|
nvidia,function = "sdmmc1";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
sdmmc1_clk_pz0 {
|
|
|
|
nvidia,pins = "sdmmc1_clk_pz0";
|
|
|
|
nvidia,function = "sdmmc1";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
lcd_wr_n_pz3 {
|
|
|
|
nvidia,pins = "lcd_wr_n_pz3";
|
|
|
|
nvidia,function = "displaya";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
sys_clk_req_pz5 {
|
|
|
|
nvidia,pins = "sys_clk_req_pz5";
|
|
|
|
nvidia,function = "sysclk";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
pwr_i2c_scl_pz6 {
|
|
|
|
nvidia,pins = "pwr_i2c_scl_pz6",
|
|
|
|
"pwr_i2c_sda_pz7";
|
|
|
|
nvidia,function = "i2cpwr";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
pbb0 {
|
|
|
|
nvidia,pins = "pbb0",
|
|
|
|
"pcc1";
|
|
|
|
nvidia,function = "rsvd2";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
cam_i2c_scl_pbb1 {
|
|
|
|
nvidia,pins = "cam_i2c_scl_pbb1",
|
|
|
|
"cam_i2c_sda_pbb2";
|
|
|
|
nvidia,function = "i2c3";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
pbb3 {
|
|
|
|
nvidia,pins = "pbb3";
|
|
|
|
nvidia,function = "vgp3";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
pbb4 {
|
|
|
|
nvidia,pins = "pbb4";
|
|
|
|
nvidia,function = "vgp4";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
pbb5 {
|
|
|
|
nvidia,pins = "pbb5";
|
|
|
|
nvidia,function = "vgp5";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
pbb6 {
|
|
|
|
nvidia,pins = "pbb6";
|
|
|
|
nvidia,function = "vgp6";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
pbb7 {
|
|
|
|
nvidia,pins = "pbb7",
|
|
|
|
"pcc2";
|
|
|
|
nvidia,function = "i2s4";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
cam_mclk_pcc0 {
|
|
|
|
nvidia,pins = "cam_mclk_pcc0";
|
|
|
|
nvidia,function = "vi_alt3";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
sdmmc4_rst_n_pcc3 {
|
|
|
|
nvidia,pins = "sdmmc4_rst_n_pcc3";
|
|
|
|
nvidia,function = "rsvd2";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
sdmmc4_clk_pcc4 {
|
|
|
|
nvidia,pins = "sdmmc4_clk_pcc4";
|
|
|
|
nvidia,function = "sdmmc4";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
clk2_req_pcc5 {
|
|
|
|
nvidia,pins = "clk2_req_pcc5";
|
|
|
|
nvidia,function = "dap";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
pex_l2_rst_n_pcc6 {
|
|
|
|
nvidia,pins = "pex_l2_rst_n_pcc6",
|
|
|
|
"pex_l2_clkreq_n_pcc7";
|
|
|
|
nvidia,function = "pcie";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
pex_wake_n_pdd3 {
|
|
|
|
nvidia,pins = "pex_wake_n_pdd3",
|
|
|
|
"pex_l2_prsnt_n_pdd7";
|
|
|
|
nvidia,function = "pcie";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
clk3_out_pee0 {
|
|
|
|
nvidia,pins = "clk3_out_pee0";
|
|
|
|
nvidia,function = "extperiph3";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
clk1_req_pee2 {
|
|
|
|
nvidia,pins = "clk1_req_pee2";
|
|
|
|
nvidia,function = "dap";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
hdmi_cec_pee3 {
|
|
|
|
nvidia,pins = "hdmi_cec_pee3";
|
|
|
|
nvidia,function = "cec";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
|
|
};
|
|
|
|
owr {
|
|
|
|
nvidia,pins = "owr";
|
|
|
|
nvidia,function = "owr";
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
};
|
|
|
|
drive_dap1 {
|
|
|
|
nvidia,pins = "drive_dap1",
|
|
|
|
"drive_dap2",
|
|
|
|
"drive_dbg",
|
|
|
|
"drive_at5",
|
|
|
|
"drive_gme",
|
|
|
|
"drive_ddc",
|
|
|
|
"drive_ao1",
|
|
|
|
"drive_uart3";
|
|
|
|
nvidia,high-speed-mode = <0>;
|
|
|
|
nvidia,schmitt = <TEGRA_PIN_ENABLE>;
|
|
|
|
nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
|
|
|
|
nvidia,pull-down-strength = <31>;
|
|
|
|
nvidia,pull-up-strength = <31>;
|
|
|
|
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
|
|
|
|
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
|
|
|
|
};
|
|
|
|
drive_sdio1 {
|
|
|
|
nvidia,pins = "drive_sdio1",
|
|
|
|
"drive_sdio3";
|
|
|
|
nvidia,high-speed-mode = <0>;
|
|
|
|
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
|
|
|
|
nvidia,pull-down-strength = <46>;
|
|
|
|
nvidia,pull-up-strength = <42>;
|
|
|
|
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
|
|
|
|
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
|
|
|
|
};
|
|
|
|
drive_gma {
|
|
|
|
nvidia,pins = "drive_gma",
|
|
|
|
"drive_gmb",
|
|
|
|
"drive_gmc",
|
|
|
|
"drive_gmd";
|
|
|
|
nvidia,pull-down-strength = <9>;
|
|
|
|
nvidia,pull-up-strength = <9>;
|
|
|
|
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
|
|
|
|
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
2023-06-30 07:29:04 +00:00
|
|
|
uarta: serial@70006000 {
|
|
|
|
status = "okay";
|
|
|
|
};
|
|
|
|
|
|
|
|
pwm: pwm@7000a000 {
|
|
|
|
status = "okay";
|
|
|
|
};
|
|
|
|
|
|
|
|
pwr_i2c: i2c@7000d000 {
|
|
|
|
status = "okay";
|
|
|
|
clock-frequency = <400000>;
|
|
|
|
};
|
|
|
|
|
|
|
|
sdmmc4: sdhci@78000600 {
|
|
|
|
status = "okay";
|
|
|
|
bus-width = <8>;
|
|
|
|
non-removable;
|
2023-10-03 06:36:41 +00:00
|
|
|
|
|
|
|
vmmc-supply = <&vcore_emmc>;
|
|
|
|
vqmmc-supply = <&vdd_1v8_vio>;
|
2023-06-30 07:29:04 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
usb1: usb@7d000000 {
|
|
|
|
status = "okay";
|
|
|
|
dr_mode = "otg";
|
|
|
|
};
|
|
|
|
|
2023-08-25 17:23:14 +00:00
|
|
|
usb-phy@7d000000 {
|
|
|
|
status = "okay";
|
|
|
|
nvidia,hssync-start-delay = <0>;
|
|
|
|
nvidia,xcvr-lsfslew = <2>;
|
|
|
|
nvidia,xcvr-lsrslew = <2>;
|
|
|
|
};
|
|
|
|
|
2023-06-30 07:29:04 +00:00
|
|
|
backlight: backlight {
|
|
|
|
compatible = "pwm-backlight";
|
|
|
|
|
|
|
|
enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
|
|
|
|
power-supply = <&vdd_5v0_bl>;
|
|
|
|
pwms = <&pwm 0 50000>;
|
|
|
|
|
|
|
|
brightness-levels = <1 35 70 105 140 175 210 255>;
|
|
|
|
default-brightness-level = <5>;
|
|
|
|
};
|
|
|
|
|
|
|
|
/* PMIC has a built-in 32KHz oscillator which is used by PMC */
|
|
|
|
clk32k_in: clock-32k {
|
|
|
|
compatible = "fixed-clock";
|
|
|
|
#clock-cells = <0>;
|
|
|
|
clock-frequency = <32768>;
|
|
|
|
clock-output-names = "pmic-oscillator";
|
|
|
|
};
|
|
|
|
|
|
|
|
gpio-keys {
|
|
|
|
compatible = "gpio-keys";
|
|
|
|
|
|
|
|
key-power {
|
|
|
|
label = "Power";
|
|
|
|
gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
|
|
|
|
linux,code = <KEY_ENTER>;
|
|
|
|
};
|
|
|
|
|
|
|
|
key-volume-up {
|
|
|
|
label = "Volume Up";
|
|
|
|
gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>;
|
|
|
|
linux,code = <KEY_UP>;
|
|
|
|
};
|
|
|
|
|
|
|
|
key-volume-down {
|
|
|
|
label = "Volume Down";
|
|
|
|
gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>;
|
|
|
|
linux,code = <KEY_DOWN>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
panel: panel {
|
|
|
|
compatible = "simple-panel";
|
|
|
|
|
|
|
|
power-supply = <&vdd_pnl_reg>;
|
|
|
|
enable-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_HIGH>;
|
|
|
|
|
|
|
|
backlight = <&backlight>;
|
|
|
|
|
|
|
|
display-timings {
|
|
|
|
timing@0 {
|
|
|
|
/* 1280x800@60Hz */
|
|
|
|
clock-frequency = <68000000>;
|
|
|
|
|
|
|
|
hactive = <800>;
|
|
|
|
hfront-porch = <24>;
|
|
|
|
hback-porch = <32>;
|
|
|
|
hsync-len = <24>;
|
|
|
|
|
|
|
|
vactive = <1280>;
|
|
|
|
vfront-porch = <5>;
|
|
|
|
vback-porch = <32>;
|
|
|
|
vsync-len = <1>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
vdd_pnl_reg: regulator-pnl {
|
|
|
|
compatible = "regulator-fixed";
|
|
|
|
regulator-name = "vdd_panel";
|
|
|
|
regulator-min-microvolt = <3300000>;
|
|
|
|
regulator-max-microvolt = <3300000>;
|
|
|
|
gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>;
|
|
|
|
enable-active-high;
|
|
|
|
};
|
|
|
|
|
|
|
|
vdd_5v0_bl: regulator-bl {
|
|
|
|
compatible = "regulator-fixed";
|
|
|
|
regulator-name = "vdd_5v0_bl";
|
|
|
|
regulator-min-microvolt = <5000000>;
|
|
|
|
regulator-max-microvolt = <5000000>;
|
|
|
|
gpio = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
|
|
|
|
enable-active-high;
|
|
|
|
};
|
|
|
|
};
|