u-boot/arch/arm/include/asm/arch-armv7/systimer.h

/*
 * (C) Copyright 2010 Linaro
 * Matt Waddel, <matt.waddel@linaro.org>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#ifndef _SYSTIMER_H_
#define _SYSTIMER_H_

/* AMBA timer register base address */
#define SYSTIMER_BASE		0x10011000

#define SYSHZ_CLOCK		1000000		/* Timers -> 1Mhz */
#define SYSTIMER_RELOAD		0xFFFFFFFF
#define SYSTIMER_EN		(1 << 7)
#define SYSTIMER_32BIT		(1 << 1)
#define SYSTIMER_PRESC_16	(1 << 2)
#define SYSTIMER_PRESC_256	(1 << 3)

struct systimer {
	u32 timer0load;		/* 0x00 */
	u32 timer0value;
	u32 timer0control;
	u32 timer0intclr;
	u32 timer0ris;
	u32 timer0mis;
	u32 timer0bgload;
	u32 timer1load;		/* 0x20 */
	u32 timer1value;
	u32 timer1control;
	u32 timer1intclr;
	u32 timer1ris;
	u32 timer1mis;
	u32 timer1bgload;
};
#endif /* _SYSTIMER_H_ */
ARMV7: Versatile Express Coretile CortexA9x4 support Adds support for the ARM quad-core Cortex-A9 processor This system includes a motherboard(Versatile Express), daughterboard (Coretile), and SOC(Cortex-A9 quad core). The serial port, ethernet, and flash systems work with these additions. The naming convention is: SOC -> CortexA9 quad core = ca9x4 daughterboard -> Coretile = ct motherboard -> Versatile Express = vxp This gives ca9x4_ct_vxp.c as the board support file. Signed-off-by: Matt Waddel <matt.waddel@linaro.org> 2010-10-07 21:48:45 +00:00			`/*`
			`* (C) Copyright 2010 Linaro`
			`* Matt Waddel, <matt.waddel@linaro.org>`
			`*`
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> 2013-07-08 07:37:19 +00:00			`* SPDX-License-Identifier: GPL-2.0+`
ARMV7: Versatile Express Coretile CortexA9x4 support Adds support for the ARM quad-core Cortex-A9 processor This system includes a motherboard(Versatile Express), daughterboard (Coretile), and SOC(Cortex-A9 quad core). The serial port, ethernet, and flash systems work with these additions. The naming convention is: SOC -> CortexA9 quad core = ca9x4 daughterboard -> Coretile = ct motherboard -> Versatile Express = vxp This gives ca9x4_ct_vxp.c as the board support file. Signed-off-by: Matt Waddel <matt.waddel@linaro.org> 2010-10-07 21:48:45 +00:00			`*/`
			`#ifndef _SYSTIMER_H_`
			`#define _SYSTIMER_H_`

			`/* AMBA timer register base address */`
			`#define SYSTIMER_BASE 0x10011000`

			`#define SYSHZ_CLOCK 1000000 /* Timers -> 1Mhz */`
			`#define SYSTIMER_RELOAD 0xFFFFFFFF`
			`#define SYSTIMER_EN (1 << 7)`
			`#define SYSTIMER_32BIT (1 << 1)`
ARM: highbank: set timer prescaler to 256 The 150MHz clock rate gives u-boot time functions problems and there's no benefit to a fast clock, so lower the rate. Signed-off-by: Rob Herring <rob.herring@calxeda.com> 2013-06-13 03:24:49 +00:00			`#define SYSTIMER_PRESC_16 (1 << 2)`
			`#define SYSTIMER_PRESC_256 (1 << 3)`
ARMV7: Versatile Express Coretile CortexA9x4 support Adds support for the ARM quad-core Cortex-A9 processor This system includes a motherboard(Versatile Express), daughterboard (Coretile), and SOC(Cortex-A9 quad core). The serial port, ethernet, and flash systems work with these additions. The naming convention is: SOC -> CortexA9 quad core = ca9x4 daughterboard -> Coretile = ct motherboard -> Versatile Express = vxp This gives ca9x4_ct_vxp.c as the board support file. Signed-off-by: Matt Waddel <matt.waddel@linaro.org> 2010-10-07 21:48:45 +00:00
			`struct systimer {`
			`u32 timer0load; /* 0x00 */`
			`u32 timer0value;`
			`u32 timer0control;`
			`u32 timer0intclr;`
			`u32 timer0ris;`
			`u32 timer0mis;`
			`u32 timer0bgload;`
			`u32 timer1load; /* 0x20 */`
			`u32 timer1value;`
			`u32 timer1control;`
			`u32 timer1intclr;`
			`u32 timer1ris;`
			`u32 timer1mis;`
			`u32 timer1bgload;`
			`};`
			`#endif /* _SYSTIMER_H_ */`