mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-30 00:21:06 +00:00
68 lines
1.3 KiB
C
68 lines
1.3 KiB
C
|
// SPDX-License-Identifier: GPL-2.0+
|
||
|
|
/*
|
||
|
|
* Copyright 2020 Compass Electronics Group, LLC
|
||
|
|
*/
|
||
|
|
|
||
|
|
#include <common.h>
|
||
|
|
#include <miiphy.h>
|
||
|
|
#include <netdev.h>
|
||
|
|
|
||
|
|
#include <asm/arch/clock.h>
|
||
|
|
#include <asm/arch/sys_proto.h>
|
||
|
|
#include <asm/io.h>
|
||
|
|
|
||
|
|
DECLARE_GLOBAL_DATA_PTR;
|
||
|
|
|
||
|
|
int dram_init(void)
|
||
|
|
{
|
||
|
|
/* rom_pointer[1] contains the size of TEE occupies */
|
||
|
|
if (rom_pointer[1])
|
||
|
|
gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
|
||
|
|
else
|
||
|
|
gd->ram_size = PHYS_SDRAM_SIZE;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
#if IS_ENABLED(CONFIG_FEC_MXC)
|
||
|
|
static int setup_fec(void)
|
||
|
|
{
|
||
|
|
struct iomuxc_gpr_base_regs *gpr =
|
||
|
|
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
|
||
|
|
|
||
|
|
/* Use 125M anatop REF_CLK1 for ENET1, not from external */
|
||
|
|
clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
int board_phy_config(struct phy_device *phydev)
|
||
|
|
{
|
||
|
|
/* enable rgmii rxc skew and phy mode select to RGMII copper */
|
||
|
|
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
|
||
|
|
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
|
||
|
|
|
||
|
|
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
|
||
|
|
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
|
||
|
|
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
|
||
|
|
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
|
||
|
|
|
||
|
|
if (phydev->drv->config)
|
||
|
|
phydev->drv->config(phydev);
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
int board_init(void)
|
||
|
|
{
|
||
|
|
if (IS_ENABLED(CONFIG_FEC_MXC))
|
||
|
|
setup_fec();
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
int board_mmc_get_env_dev(int devno)
|
||
|
|
{
|
||
|
|
return devno;
|
||
|
|
}
|