2020-06-30 10:08:56 +00:00
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 Stefan Roese <sr@denx.de>
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*/
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#include <config.h>
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#include <asm-offsets.h>
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#include <asm/cacheops.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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#include <asm/addrspace.h>
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#include <asm/asm.h>
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.set noreorder
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LEAF(lowlevel_init)
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jr ra
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nop
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END(lowlevel_init)
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2020-06-30 10:33:17 +00:00
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LEAF(mips_mach_early_init)
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move s0, ra
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bal __dummy
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nop
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__dummy:
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/* Get the actual address that we are running at */
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PTR_LA a7, __dummy
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dsubu t3, ra, a7 /* t3 now has reloc offset */
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PTR_LA t1, _start
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daddu t0, t1, t3 /* t0 now has actual address of _start */
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/* Calculate end address of copy loop */
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PTR_LA t2, _end
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daddiu t2, t2, 0x4000 /* Increase size to include appended DTB */
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daddiu t2, t2, 127
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ins t2, zero, 0, 7 /* Round up to cache line for memcpy */
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/* Copy ourself to the L2 cache from flash, 32 bytes at a time */
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1:
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ld a0, 0(t0)
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ld a1, 8(t0)
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ld a2, 16(t0)
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ld a3, 24(t0)
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sd a0, 0(t1)
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sd a1, 8(t1)
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sd a2, 16(t1)
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sd a3, 24(t1)
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addiu t0, 32
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addiu t1, 32
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bne t1, t2, 1b
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nop
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sync
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/*
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* Return to start.S now running from TEXT_BASE, which points
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* to DRAM address space, which effectively is L2 cache now.
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* This speeds up the init process extremely, especially the
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* DDR init code.
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*/
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dsubu s0, s0, t3 /* Fixup return address with reloc offset */
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jr.hb s0 /* Jump back with hazard barrier */
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nop
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END(mips_mach_early_init)
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