u-boot/arch/arm/dts/fsl-ls1028a-rdb.dts

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// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP ls1028ARDB device tree source
*
* Copyright 2019 NXP
*
*/
/dts-v1/;
#include "fsl-ls1028a.dtsi"
/ {
model = "NXP Layerscape 1028a RDB Board";
compatible = "fsl,ls1028a-rdb", "fsl,ls1028a";
aliases {
spi0 = &fspi;
eth0 = &enetc0;
eth1 = &enetc2;
eth2 = &mscc_felix_port0;
eth3 = &mscc_felix_port1;
eth4 = &mscc_felix_port2;
eth5 = &mscc_felix_port3;
};
};
&dspi0 {
status = "okay";
};
&dspi1 {
status = "okay";
};
&dspi2 {
status = "okay";
};
&esdhc0 {
status = "okay";
};
&esdhc1 {
status = "okay";
mmc-hs200-1_8v;
};
&fspi {
status = "okay";
mt35xu02g0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
spi-rx-bus-width = <8>;
spi-tx-bus-width = <1>;
};
};
&i2c0 {
status = "okay";
u-boot,dm-pre-reloc;
i2c-mux@77 {
compatible = "nxp,pca9547";
reg = <0x77>;
#address-cells = <1>;
#size-cells = <0>;
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
rtc@51 {
compatible = "pcf2127-rtc";
reg = <0x51>;
};
};
};
};
&i2c1 {
status = "okay";
};
&i2c2 {
status = "okay";
};
&i2c3 {
status = "okay";
};
&i2c4 {
status = "okay";
};
&i2c5 {
status = "okay";
};
&i2c6 {
status = "okay";
};
&i2c7 {
status = "okay";
};
&sata {
status = "okay";
};
&serial0 {
status = "okay";
};
&serial1 {
status = "okay";
};
&usb1 {
status = "okay";
};
&usb2 {
status = "okay";
};
&enetc0 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&rdb_phy0>;
};
&enetc2 {
status = "okay";
};
&mscc_felix {
status = "okay";
};
&mscc_felix_port0 {
label = "swp0";
phy-handle = <&sw_phy0>;
phy-mode = "qsgmii";
status = "okay";
};
&mscc_felix_port1 {
label = "swp1";
phy-handle = <&sw_phy1>;
phy-mode = "qsgmii";
status = "okay";
};
&mscc_felix_port2 {
label = "swp2";
phy-handle = <&sw_phy2>;
phy-mode = "qsgmii";
status = "okay";
};
&mscc_felix_port3 {
label = "swp3";
phy-handle = <&sw_phy3>;
phy-mode = "qsgmii";
status = "okay";
};
&mscc_felix_port4 {
ethernet = <&enetc2>;
status = "okay";
};
&mdio0 {
status = "okay";
rdb_phy0: phy@2 {
reg = <2>;
};
/* VSC8514 QSGMII PHY */
sw_phy0: phy@10 {
reg = <0x10>;
};
sw_phy1: phy@11 {
reg = <0x11>;
};
sw_phy2: phy@12 {
reg = <0x12>;
};
sw_phy3: phy@13 {
reg = <0x13>;
};
};