2014-11-15 01:18:32 +00:00
|
|
|
/*
|
|
|
|
* Copyright (C) 2014 Google, Inc
|
|
|
|
*
|
|
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
|
|
*/
|
|
|
|
#include <common.h>
|
2015-03-05 19:25:33 +00:00
|
|
|
#include <dm.h>
|
2014-11-15 01:18:32 +00:00
|
|
|
#include <errno.h>
|
|
|
|
#include <fdtdec.h>
|
|
|
|
#include <malloc.h>
|
2016-01-19 03:19:21 +00:00
|
|
|
#include <pch.h>
|
2014-11-15 01:18:32 +00:00
|
|
|
#include <asm/lapic.h>
|
|
|
|
#include <asm/pci.h>
|
|
|
|
#include <asm/arch/bd82x6x.h>
|
|
|
|
#include <asm/arch/model_206ax.h>
|
|
|
|
#include <asm/arch/pch.h>
|
|
|
|
#include <asm/arch/sandybridge.h>
|
|
|
|
|
2016-01-19 03:19:21 +00:00
|
|
|
#define BIOS_CTRL 0xdc
|
|
|
|
|
2015-03-05 19:25:33 +00:00
|
|
|
static int bd82x6x_probe(struct udevice *dev)
|
2014-11-15 01:18:32 +00:00
|
|
|
{
|
2014-11-15 01:18:38 +00:00
|
|
|
const void *blob = gd->fdt_blob;
|
2016-01-17 23:11:37 +00:00
|
|
|
int gma_node;
|
2014-11-15 03:56:36 +00:00
|
|
|
int ret;
|
2014-11-15 01:18:35 +00:00
|
|
|
|
2016-01-17 23:11:10 +00:00
|
|
|
if (!(gd->flags & GD_FLG_RELOC))
|
|
|
|
return 0;
|
|
|
|
|
2016-01-17 23:11:37 +00:00
|
|
|
/* Cause the SATA device to do its init */
|
|
|
|
uclass_first_device(UCLASS_DISK, &dev);
|
|
|
|
|
2014-11-15 01:18:40 +00:00
|
|
|
bd82x6x_usb_ehci_init(PCH_EHCI1_DEV);
|
|
|
|
bd82x6x_usb_ehci_init(PCH_EHCI2_DEV);
|
2014-11-15 01:18:35 +00:00
|
|
|
|
2014-11-15 03:56:36 +00:00
|
|
|
gma_node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_GMA);
|
|
|
|
if (gma_node < 0) {
|
|
|
|
debug("%s: Cannot find GMA node\n", __func__);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2015-11-29 20:17:55 +00:00
|
|
|
ret = dm_pci_bus_find_bdf(PCH_VIDEO_DEV, &dev);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
ret = gma_func0_init(dev, blob, gma_node);
|
2014-11-15 03:56:36 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2014-11-15 01:18:32 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-01-19 03:19:21 +00:00
|
|
|
static int bd82x6x_pch_get_sbase(struct udevice *dev, ulong *sbasep)
|
|
|
|
{
|
|
|
|
u32 rcba;
|
|
|
|
|
|
|
|
dm_pci_read_config32(dev, PCH_RCBA, &rcba);
|
|
|
|
/* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */
|
|
|
|
rcba = rcba & 0xffffc000;
|
|
|
|
*sbasep = rcba + 0x3800;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static enum pch_version bd82x6x_pch_get_version(struct udevice *dev)
|
|
|
|
{
|
|
|
|
return PCHV_9;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int bd82x6x_set_spi_protect(struct udevice *dev, bool protect)
|
|
|
|
{
|
|
|
|
uint8_t bios_cntl;
|
|
|
|
|
|
|
|
/* Adjust the BIOS write protect and SMM BIOS Write Protect Disable */
|
|
|
|
dm_pci_read_config8(dev, BIOS_CTRL, &bios_cntl);
|
|
|
|
if (protect) {
|
|
|
|
bios_cntl &= ~BIOS_CTRL_BIOSWE;
|
|
|
|
bios_cntl |= BIT(5);
|
|
|
|
} else {
|
|
|
|
bios_cntl |= BIOS_CTRL_BIOSWE;
|
|
|
|
bios_cntl &= ~BIT(5);
|
|
|
|
}
|
|
|
|
dm_pci_write_config8(dev, BIOS_CTRL, bios_cntl);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct pch_ops bd82x6x_pch_ops = {
|
|
|
|
.get_sbase = bd82x6x_pch_get_sbase,
|
|
|
|
.get_version = bd82x6x_pch_get_version,
|
|
|
|
.set_spi_protect = bd82x6x_set_spi_protect,
|
|
|
|
};
|
|
|
|
|
2015-03-05 19:25:33 +00:00
|
|
|
static const struct udevice_id bd82x6x_ids[] = {
|
|
|
|
{ .compatible = "intel,bd82x6x" },
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
U_BOOT_DRIVER(bd82x6x_drv) = {
|
|
|
|
.name = "bd82x6x",
|
|
|
|
.id = UCLASS_PCH,
|
|
|
|
.of_match = bd82x6x_ids,
|
|
|
|
.probe = bd82x6x_probe,
|
2016-01-19 03:19:21 +00:00
|
|
|
.ops = &bd82x6x_pch_ops,
|
2015-03-05 19:25:33 +00:00
|
|
|
};
|