2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2014-09-05 05:52:44 +00:00
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/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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2019-12-31 07:33:44 +00:00
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* Copyright 2019 NXP
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2014-09-05 05:52:44 +00:00
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
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#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
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2016-02-02 07:16:23 +00:00
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#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
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2014-12-09 09:38:02 +00:00
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#define CONFIG_QIXIS_I2C_ACCESS
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#endif
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2014-09-05 05:52:44 +00:00
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2014-12-03 07:00:47 +00:00
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#ifdef CONFIG_SD_BOOT
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#define CONFIG_SPL_MAX_SIZE 0x1a000
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#define CONFIG_SPL_STACK 0x1001d000
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#define CONFIG_SPL_PAD_TO 0x1c000
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2014-12-17 04:58:05 +00:00
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#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
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CONFIG_SYS_MONITOR_LEN)
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2014-12-03 07:00:47 +00:00
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
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#define CONFIG_SPL_BSS_START_ADDR 0x80100000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
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2015-10-30 14:45:38 +00:00
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#define CONFIG_SYS_MONITOR_LEN 0xc0000
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2014-12-03 07:00:47 +00:00
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#endif
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2014-12-09 09:38:14 +00:00
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#ifdef CONFIG_NAND_BOOT
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#define CONFIG_SPL_MAX_SIZE 0x1a000
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#define CONFIG_SPL_STACK 0x1001d000
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#define CONFIG_SPL_PAD_TO 0x1c000
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#define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10)
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#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
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#define CONFIG_SPL_BSS_START_ADDR 0x80100000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
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#define CONFIG_SYS_MONITOR_LEN 0x80000
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#endif
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2014-09-05 05:52:44 +00:00
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#define SPD_EEPROM_ADDRESS 0x51
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#define CONFIG_SYS_SPD_BUS_NUM 0
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2014-09-11 20:32:07 +00:00
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#ifndef CONFIG_SYS_FSL_DDR4
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#define CONFIG_SYS_DDR_RAW_TIMING
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#endif
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2014-09-05 05:52:44 +00:00
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#ifdef CONFIG_DDR_ECC
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#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
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#endif
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/*
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* IFC Definitions
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*/
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2016-02-02 07:16:23 +00:00
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#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
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2014-09-05 05:52:44 +00:00
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#define CONFIG_SYS_FLASH_BASE 0x60000000
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#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
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#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
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CSPR_PORT_SIZE_16 | \
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CSPR_MSEL_NOR | \
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CSPR_V)
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#define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
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#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
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+ 0x8000000) | \
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CSPR_PORT_SIZE_16 | \
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CSPR_MSEL_NOR | \
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CSPR_V)
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#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
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#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
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CSOR_NOR_TRHZ_80)
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#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
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FTIM0_NOR_TEADC(0x5) | \
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FTIM0_NOR_TEAHC(0x5))
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#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
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FTIM1_NOR_TRAD_NOR(0x1a) | \
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FTIM1_NOR_TSEQRAD_NOR(0x13))
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#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
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FTIM2_NOR_TCH(0x4) | \
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FTIM2_NOR_TWPH(0xe) | \
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FTIM2_NOR_TWP(0x1c))
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#define CONFIG_SYS_NOR_FTIM3 0
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#define CONFIG_SYS_FLASH_QUIET_TEST
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#define CONFIG_FLASH_SHOW_PROGRESS 45
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2014-10-17 07:26:34 +00:00
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#define CONFIG_SYS_WRITE_SWAPPED_DATA
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2014-09-05 05:52:44 +00:00
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#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
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CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
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/*
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* NAND Flash Definitions
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*/
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#define CONFIG_SYS_NAND_BASE 0x7e800000
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#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
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#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
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#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
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| CSPR_PORT_SIZE_8 \
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| CSPR_MSEL_NAND \
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| CSPR_V)
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#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
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#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
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| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
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| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
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| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
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| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
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| CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
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| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
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#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
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FTIM0_NAND_TWP(0x18) | \
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FTIM0_NAND_TWCHT(0x7) | \
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FTIM0_NAND_TWH(0xa))
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#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
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FTIM1_NAND_TWBE(0x39) | \
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FTIM1_NAND_TRR(0xe) | \
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FTIM1_NAND_TRP(0x18))
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#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
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FTIM2_NAND_TREH(0xa) | \
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FTIM2_NAND_TWHRE(0x1e))
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#define CONFIG_SYS_NAND_FTIM3 0x0
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#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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2014-12-09 09:38:02 +00:00
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#endif
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2014-09-05 05:52:44 +00:00
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/*
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* QIXIS Definitions
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*/
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#define CONFIG_FSL_QIXIS
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#ifdef CONFIG_FSL_QIXIS
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#define QIXIS_BASE 0x7fb00000
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#define QIXIS_BASE_PHYS QIXIS_BASE
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#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
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#define QIXIS_LBMAP_SWITCH 6
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#define QIXIS_LBMAP_MASK 0x0f
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#define QIXIS_LBMAP_SHIFT 0
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#define QIXIS_LBMAP_DFLTBANK 0x00
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#define QIXIS_LBMAP_ALTBANK 0x04
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2016-07-21 10:09:38 +00:00
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#define QIXIS_PWR_CTL 0x21
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#define QIXIS_PWR_CTL_POWEROFF 0x80
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2014-09-05 05:52:44 +00:00
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#define QIXIS_RST_CTL_RESET 0x44
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#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
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#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
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#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
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2016-08-19 09:20:31 +00:00
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#define QIXIS_CTL_SYS 0x5
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#define QIXIS_CTL_SYS_EVTSW_MASK 0x0c
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#define QIXIS_CTL_SYS_EVTSW_IRQ 0x04
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#define QIXIS_RST_FORCE_3 0x45
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#define QIXIS_RST_FORCE_3_PCIESLOT1 0x80
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#define QIXIS_PWR_CTL2 0x21
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#define QIXIS_PWR_CTL2_PCTL 0x2
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2014-09-05 05:52:44 +00:00
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#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
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#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
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CSPR_PORT_SIZE_8 | \
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CSPR_MSEL_GPCM | \
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CSPR_V)
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#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
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#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
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CSOR_NOR_NOR_MODE_AVD_NOR | \
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CSOR_NOR_TRHZ_80)
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/*
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* QIXIS Timing parameters for IFC GPCM
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*/
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#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \
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FTIM0_GPCM_TEADC(0xe) | \
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FTIM0_GPCM_TEAHC(0xe))
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#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \
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FTIM1_GPCM_TRAD(0x1f))
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#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \
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FTIM2_GPCM_TCH(0xe) | \
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FTIM2_GPCM_TWP(0xf0))
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#define CONFIG_SYS_FPGA_FTIM3 0x0
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#endif
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2014-12-09 09:38:14 +00:00
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#if defined(CONFIG_NAND_BOOT)
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#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
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#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
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#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
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#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
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#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
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#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
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#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
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#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
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#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
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#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
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#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
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#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
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#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
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#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
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#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
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#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
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#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
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#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
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#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
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#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
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#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
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#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
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#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
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#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
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#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
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#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
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#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
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#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
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#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
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#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
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#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
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#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
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#else
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2014-09-05 05:52:44 +00:00
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#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
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#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
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#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
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#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
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#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
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#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
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#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
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#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
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#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
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#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
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#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
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#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
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#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
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#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
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#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
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#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
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#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
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#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
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#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
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#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
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#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
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#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
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#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
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#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
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#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
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#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
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#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
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#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
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#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
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#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
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#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
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#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
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2014-12-09 09:38:14 +00:00
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#endif
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2014-09-05 05:52:44 +00:00
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/*
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* Serial Port
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*/
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2022-03-23 21:20:00 +00:00
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#ifndef CONFIG_LPUART
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2014-09-05 05:52:44 +00:00
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#define CONFIG_SYS_NS16550_SERIAL
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2016-02-08 21:04:17 +00:00
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#ifndef CONFIG_DM_SERIAL
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2014-09-05 05:52:44 +00:00
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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2016-02-08 21:04:17 +00:00
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#endif
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2014-09-05 05:52:44 +00:00
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#define CONFIG_SYS_NS16550_CLK get_serial_clock()
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2015-01-04 07:30:58 +00:00
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#endif
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2014-09-05 05:52:44 +00:00
|
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|
|
|
/*
|
|
|
|
* I2C
|
|
|
|
*/
|
|
|
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2021-02-05 11:02:03 +00:00
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|
|
/* GPIO */
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|
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|
2018-05-09 22:34:29 +00:00
|
|
|
/* EEPROM */
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|
|
|
#define CONFIG_SYS_I2C_EEPROM_NXID
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|
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|
#define CONFIG_SYS_EEPROM_BUS_NUM 0
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|
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|
2014-09-05 05:52:44 +00:00
|
|
|
/*
|
|
|
|
* I2C bus multiplexer
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|
|
|
*/
|
|
|
|
#define I2C_MUX_PCA_ADDR_PRI 0x77
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|
|
#define I2C_MUX_CH_DEFAULT 0x8
|
2014-12-16 06:50:33 +00:00
|
|
|
#define I2C_MUX_CH_CH7301 0xC
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2014-09-05 05:52:44 +00:00
|
|
|
|
|
|
|
/*
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|
|
|
* MMC
|
|
|
|
*/
|
|
|
|
|
|
|
|
/*
|
|
|
|
* eTSEC
|
|
|
|
*/
|
|
|
|
|
|
|
|
#ifdef CONFIG_TSEC_ENET
|
|
|
|
#define CONFIG_MII_DEFAULT_TSEC 3
|
|
|
|
#define CONFIG_TSEC1 1
|
|
|
|
#define CONFIG_TSEC1_NAME "eTSEC1"
|
|
|
|
#define CONFIG_TSEC2 1
|
|
|
|
#define CONFIG_TSEC2_NAME "eTSEC2"
|
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|
|
#define CONFIG_TSEC3 1
|
|
|
|
#define CONFIG_TSEC3_NAME "eTSEC3"
|
|
|
|
|
|
|
|
#define TSEC1_PHY_ADDR 1
|
|
|
|
#define TSEC2_PHY_ADDR 2
|
|
|
|
#define TSEC3_PHY_ADDR 3
|
|
|
|
|
|
|
|
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
|
|
|
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
|
|
|
#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
|
|
|
|
|
|
|
#define TSEC1_PHYIDX 0
|
|
|
|
#define TSEC2_PHYIDX 0
|
|
|
|
#define TSEC3_PHYIDX 0
|
|
|
|
|
|
|
|
#define CONFIG_FSL_SGMII_RISER 1
|
|
|
|
#define SGMII_RISER_PHY_OFFSET 0x1b
|
|
|
|
|
|
|
|
#ifdef CONFIG_FSL_SGMII_RISER
|
|
|
|
#define CONFIG_SYS_TBIPA_VALUE 8
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#endif
|
2014-10-31 05:43:44 +00:00
|
|
|
|
|
|
|
/* PCIe */
|
2016-05-03 23:52:49 +00:00
|
|
|
#define CONFIG_PCIE1 /* PCIE controller 1 */
|
|
|
|
#define CONFIG_PCIE2 /* PCIE controller 2 */
|
2014-10-31 05:43:44 +00:00
|
|
|
|
2015-01-21 09:29:19 +00:00
|
|
|
#ifdef CONFIG_PCI
|
|
|
|
#define CONFIG_PCI_SCAN_SHOW
|
|
|
|
#endif
|
|
|
|
|
2014-11-21 09:40:57 +00:00
|
|
|
#define CONFIG_PEN_ADDR_BIG_ENDIAN
|
2015-10-26 11:47:41 +00:00
|
|
|
#define CONFIG_LAYERSCAPE_NS_ACCESS
|
2014-11-21 09:40:57 +00:00
|
|
|
#define CONFIG_SMP_PEN_ADDR 0x01ee0200
|
2017-02-16 01:20:19 +00:00
|
|
|
#define COUNTER_FREQUENCY 12500000
|
2014-11-21 09:40:57 +00:00
|
|
|
|
2014-09-05 05:52:44 +00:00
|
|
|
#define CONFIG_HWCONFIG
|
2015-08-17 10:55:12 +00:00
|
|
|
#define HWCONFIG_BUFFER_SIZE 256
|
|
|
|
|
|
|
|
#define CONFIG_FSL_DEVICE_DISABLE
|
2014-09-05 05:52:44 +00:00
|
|
|
|
2015-01-04 07:30:58 +00:00
|
|
|
#ifdef CONFIG_LPUART
|
|
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
|
|
"bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
|
2015-11-05 03:16:26 +00:00
|
|
|
"initrd_high=0xffffffff\0" \
|
2015-01-04 07:30:58 +00:00
|
|
|
"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
|
|
|
|
#else
|
2014-09-05 05:52:44 +00:00
|
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
|
|
"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
|
2015-11-05 03:16:26 +00:00
|
|
|
"initrd_high=0xffffffff\0" \
|
2014-09-05 05:52:44 +00:00
|
|
|
"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
|
2015-01-04 07:30:58 +00:00
|
|
|
#endif
|
2014-09-05 05:52:44 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Miscellaneous configurable options
|
|
|
|
*/
|
2020-02-03 07:25:19 +00:00
|
|
|
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
|
2014-09-05 05:52:44 +00:00
|
|
|
|
2014-11-21 09:40:59 +00:00
|
|
|
#define CONFIG_LS102XA_STREAM_ID
|
|
|
|
|
2014-09-05 05:52:44 +00:00
|
|
|
#define CONFIG_SYS_INIT_SP_OFFSET \
|
|
|
|
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
|
|
|
#define CONFIG_SYS_INIT_SP_ADDR \
|
|
|
|
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Environment
|
|
|
|
*/
|
|
|
|
|
2016-01-22 11:07:22 +00:00
|
|
|
#include <asm/fsl_secure_boot.h>
|
2016-01-15 07:29:32 +00:00
|
|
|
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
|
2014-10-15 06:09:06 +00:00
|
|
|
|
2014-09-05 05:52:44 +00:00
|
|
|
#endif
|