2022-06-17 10:47:20 +00:00
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright 2022 Google LLC
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*/
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#ifndef __SOCFGPA_CHAMELEONV3_H__
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#define __SOCFGPA_CHAMELEONV3_H__
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#include <asm/arch/base_addr_a10.h>
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/*
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* U-Boot general configurations
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*/
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/* Memory configurations */
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#define PHYS_SDRAM_1_SIZE 0x40000000
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/*
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* Serial / UART configurations
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*/
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
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2022-06-17 10:47:20 +00:00
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"autoload=no\0" \
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"bootargs=cma=256M console=ttyS1,115200 root=/dev/mmcblk0p3 rw rootwait\0" \
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"distro_bootcmd=bridge enable; run bootcmd_mmc\0" \
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"bootcmd_mmc=load mmc 0:1 ${loadaddr} kernel.itb; bootm\0" \
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"bootcmd_net=dhcp; tftpboot ${loadaddr} kernel.itb; bootm\0"
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/*
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* L4 OSC1 Timer 0
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*/
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/* reload value when timer count to zero */
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#define TIMER_LOAD_VAL 0xFFFFFFFF
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/* The rest of the configuration is shared */
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#include <configs/socfpga_common.h>
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#endif /* __SOCFGPA_CHAMELEONV3_H__ */
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