u-boot/arch/riscv/cpu/generic/Kconfig

# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>

config GENERIC_RISCV
	bool
	select BINMAN if SPL
	select ARCH_EARLY_INIT_R
	imply CPU
	imply CPU_RISCV
	imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
	imply RISCV_ACLINT if RISCV_MMODE
	imply SPL_RISCV_ACLINT if SPL_RISCV_MMODE
	imply CMD_CPU
	imply SPL_CPU
	imply SPL_OPENSBI
	imply SPL_LOAD_FIT
riscv: qemu: Add platform-specific Kconfig options Add the QEMU RISC-V platform-specific Kconfig options, to include CPU and timer drivers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org> 2018-12-12 14:12:32 +00:00			`# SPDX-License-Identifier: GPL-2.0+`
			`#`
			`# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>`

riscv: Rename cpu/qemu to cpu/generic The QEMU CPU support under arch/riscv is pretty much generic and works fine for SiFive Unleashed as well. In fact, there will be quite a few RISC-V SOCs for which QEMU CPU support will work fine. This patch renames cpu/qemu to cpu/generic to indicate the above fact. If there are SOC specific errata workarounds required in cpu/generic then those can be done at runtime in cpu/generic based on CPU vendor specific DT compatible string. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 2019-02-25 08:14:10 +00:00			`config GENERIC_RISCV`
riscv: qemu: Add platform-specific Kconfig options Add the QEMU RISC-V platform-specific Kconfig options, to include CPU and timer drivers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org> 2018-12-12 14:12:32 +00:00			`bool`
riscv: qemu: Switch to use binman to generate u-boot.itb By utilizing the newly introduced BINMAN_STANDALONE_FDT option, along with a new dedicated device tree source file for the QEMU virt target used for binman only, we can now use binman to generate u-boot.itb. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> 2021-05-10 12:23:39 +00:00			`select BINMAN if SPL`
riscv: Probe cpus during boot This calls cpu_probe_all() to probe all available cpus. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org> 2018-12-12 14:12:34 +00:00			`select ARCH_EARLY_INIT_R`
riscv: qemu: Add platform-specific Kconfig options Add the QEMU RISC-V platform-specific Kconfig options, to include CPU and timer drivers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org> 2018-12-12 14:12:32 +00:00			`imply CPU`
			`imply CPU_RISCV`
riscv: Rework riscv timer driver to only support S-mode The riscv-timer driver currently serves as a shim for several riscv timer drivers. This is not too desirable because it bypasses the usual timer selection via the driver model. There is no easy way to specify an alternate timing driver, or have the tick rate depend on the cpu's configured frequency. The timer drivers also do not have device structs, and so have to rely on storing parameters in gd_t. Lastly, there is no initialization call, so driver init is done in the same function which reads the time. This can result in confusing error messages. To a user, it looks like the driver failed when trying to read the time, whereas it may have failed while initializing. This patch removes the shim functionality from the riscv-timer driver, and has it instead implement the former rdtime.c timer driver. This is because existing u-boot users who pass in a device tree (e.g. qemu) do not create a timer device for S-mode u-boot. The existing behavior of creating the riscv-timer device in the riscv cpu driver must be kept. The actual reading of the CSRs has been redone in the style of Linux's get_cycles64. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com> 2020-09-28 14:52:21 +00:00			`imply RISCV_TIMER if (RISCV_SMODE \|\| SPL_RISCV_SMODE)`
riscv: Rename SiFive CLINT to RISC-V ALINT As the RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V ALINT in the source tree to be future-proof. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com> 2023-06-21 15:11:46 +00:00			`imply RISCV_ACLINT if RISCV_MMODE`
			`imply SPL_RISCV_ACLINT if SPL_RISCV_MMODE`
riscv: qemu: Add platform-specific Kconfig options Add the QEMU RISC-V platform-specific Kconfig options, to include CPU and timer drivers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org> 2018-12-12 14:12:32 +00:00			`imply CMD_CPU`
cpu: Rename SPL_CPU_SUPPORT to SPL_CPU The _SUPPORT suffix is from an earlier time and interferes with use of the CONFIG_IS_ENABLED() macro. Rename the option to drop the suffix. Tidy up the TODO that prompted this. Signed-off-by: Simon Glass <sjg@chromium.org> 2021-03-15 05:11:18 +00:00			`imply SPL_CPU`
riscv: add SPL support U-Boot SPL on the generic RISC-V CPU supports two boot flows, directly jumping to the image and via OpenSBI firmware. In the first case, both U-Boot SPL and proper must be compiled to run in the same privilege mode. Using OpenSBI firmware, U-Boot SPL must be compiled for machine mode and U-Boot proper for supervisor mode. To be able to use SPL, boards have to provide a supported SPL boot device. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> 2019-08-21 19:14:45 +00:00			`imply SPL_OPENSBI`
			`imply SPL_LOAD_FIT`