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u-boot/arch/arm/mach-uniphier/clk/pll-ld20.c

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SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
// SPDX-License-Identifier: GPL-2.0+
ARM: uniphier: add PLL init code for LD20 SoC Initialize the DPLL (PLL for DRAM) in SPL, and others in U-Boot proper. Split the common code into pll-base-ld20.c for easier re-use. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-16 18:33:11 +00:00
/*
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*/
ARM: uniphier: replace <common.h> with <linux/delay.h> in pll settings The #include <common.h> was added for mdelay(). Later, the declaration of mdelay was moved to <linux/delay.h> by commit 5bc516ed661a ("delay: collect {m, n, u}delay declarations to include/linux/delay.h"). There is no need to include <common.h> now. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-26 08:57:58 +00:00
#include <linux/delay.h>
ARM: uniphier: add PLL init code for LD20 SoC Initialize the DPLL (PLL for DRAM) in SPL, and others in U-Boot proper. Split the common code into pll-base-ld20.c for easier re-use. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-16 18:33:11 +00:00
#include "../init.h"
#include "../sc64-regs.h"
#include "pll.h"
ARM: uniphier: move PLLCTRL register macros to each SoC .c file The new SoC PXs3 changed the address of PLL, but still uses the same PLL name. We can not define SC_*PLLCTRL in the common header. Move them to per-SoC .c file. Also, fix some PLL comments. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-26 08:57:59 +00:00
/* PLL type: SSC */
ARM: uniphier: de-couple SC macros into base address and offset The SC_* macros represent the address of SysCtrl registers. For a planned new SoC, its base address will be changed. Turn the SC_* macros into the offset from the base address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 11:07:41 +00:00
#define SC_CPLLCTRL 0x1400 /* CPU/ARM */
#define SC_SPLLCTRL 0x1410 /* misc */
#define SC_SPLL2CTRL 0x1420 /* DSP */
#define SC_MPLLCTRL 0x1430 /* Video codec */
#define SC_VPPLLCTRL 0x1440 /* VPE etc. */
#define SC_GPPLLCTRL 0x1450 /* GPU/Mali */
#define SC_DPLL0CTRL 0x1460 /* DDR memory 0 */
#define SC_DPLL1CTRL 0x1470 /* DDR memory 1 */
#define SC_DPLL2CTRL 0x1480 /* DDR memory 2 */
ARM: uniphier: move PLLCTRL register macros to each SoC .c file The new SoC PXs3 changed the address of PLL, but still uses the same PLL name. We can not define SC_*PLLCTRL in the common header. Move them to per-SoC .c file. Also, fix some PLL comments. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-26 08:57:59 +00:00
/* PLL type: VPLL27 */
ARM: uniphier: de-couple SC macros into base address and offset The SC_* macros represent the address of SysCtrl registers. For a planned new SoC, its base address will be changed. Turn the SC_* macros into the offset from the base address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 11:07:41 +00:00
#define SC_VPLL27FCTRL 0x1500
#define SC_VPLL27ACTRL 0x1520
ARM: uniphier: move PLLCTRL register macros to each SoC .c file The new SoC PXs3 changed the address of PLL, but still uses the same PLL name. We can not define SC_*PLLCTRL in the common header. Move them to per-SoC .c file. Also, fix some PLL comments. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-26 08:57:59 +00:00
/* PLL type: DSPLL */
ARM: uniphier: de-couple SC macros into base address and offset The SC_* macros represent the address of SysCtrl registers. For a planned new SoC, its base address will be changed. Turn the SC_* macros into the offset from the base address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 11:07:41 +00:00
#define SC_VPLL8KCTRL 0x1540
#define SC_A2PLLCTRL 0x15C0
ARM: uniphier: move PLLCTRL register macros to each SoC .c file The new SoC PXs3 changed the address of PLL, but still uses the same PLL name. We can not define SC_*PLLCTRL in the common header. Move them to per-SoC .c file. Also, fix some PLL comments. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-26 08:57:59 +00:00
ARM: uniphier: remove unneeded argument of uniphier_ld20_pll_init() At first, we thought the LD20 PLL setting would be board dependent, but this argument turned out unneeded after all. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-01-15 05:59:02 +00:00
void uniphier_ld20_pll_init(void)
ARM: uniphier: add PLL init code for LD20 SoC Initialize the DPLL (PLL for DRAM) in SPL, and others in U-Boot proper. Split the common code into pll-base-ld20.c for easier re-use. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-16 18:33:11 +00:00
{
uniphier_ld20_sscpll_init(SC_CPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
/* do nothing for SPLL */
uniphier_ld20_sscpll_init(SC_SPLL2CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
uniphier_ld20_sscpll_init(SC_MPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
uniphier_ld20_sscpll_init(SC_VPPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
uniphier_ld20_sscpll_init(SC_GPPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
mdelay(1);
ARM: uniphier: enable SSC for more PLLs for LD20 SoC For Electro-Magnetic Compatibility. Set CPLL, SPLL2, MPLL, VPPLL, GPPLL, DPLL* to SSC rate 1 percent. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-27 14:47:00 +00:00
uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL);
uniphier_ld20_sscpll_ssc_en(SC_SPLL2CTRL);
uniphier_ld20_sscpll_ssc_en(SC_MPLLCTRL);
uniphier_ld20_sscpll_ssc_en(SC_VPPLLCTRL);
uniphier_ld20_sscpll_ssc_en(SC_GPPLLCTRL);
uniphier_ld20_sscpll_ssc_en(SC_DPLL0CTRL);
uniphier_ld20_sscpll_ssc_en(SC_DPLL1CTRL);
uniphier_ld20_sscpll_ssc_en(SC_DPLL2CTRL);
ARM: uniphier: add PLL init code for LD20 SoC Initialize the DPLL (PLL for DRAM) in SPL, and others in U-Boot proper. Split the common code into pll-base-ld20.c for easier re-use. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-16 18:33:11 +00:00
uniphier_ld20_vpll27_init(SC_VPLL27FCTRL);
uniphier_ld20_vpll27_init(SC_VPLL27ACTRL);
uniphier_ld20_dspll_init(SC_VPLL8KCTRL);
uniphier_ld20_dspll_init(SC_A2PLLCTRL);
}
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