u-boot/arch/arm/mach-socfpga/include/mach/base_addr_a10.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) 2014-2017 Altera Corporation <www.altera.com>
 */

#ifndef _SOCFPGA_A10_BASE_HARDWARE_H_
#define _SOCFPGA_A10_BASE_HARDWARE_H_

#define SOCFPGA_EMAC0_ADDRESS			0xff800000
#define SOCFPGA_EMAC1_ADDRESS			0xff802000
#define SOCFPGA_EMAC2_ADDRESS			0xff804000
#define SOCFPGA_SDMMC_ADDRESS			0xff808000
#define SOCFPGA_QSPIREGS_ADDRESS		0xff809000
#define SOCFPGA_QSPIDATA_ADDRESS		0xffa00000
#define SOCFPGA_UART1_ADDRESS			0xffc02100
#define SOCFPGA_HMC_MMR_IO48_ADDRESS		0xffcfa000
#define SOCFPGA_FPGAMGRDATA_ADDRESS		0xffcfe400
#define SOCFPGA_FPGAMGRREGS_ADDRESS		0xffd03000
#define SOCFPGA_L4WD0_ADDRESS			0xffd00200
#define SOCFPGA_SYSMGR_ADDRESS			0xffd06000
#define SOCFPGA_PINMUX_SHARED_3V_IO_ADDRESS	0xffd07000
#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS	0xffd07200
#define SOCFPGA_PINMUX_DEDICATED_IO_CFG_ADDRESS	0xffd07300
#define SOCFPGA_PINMUX_FPGA_INTERFACE_ADDRESS	0xffd07400
#define SOCFPGA_DMANONSECURE_ADDRESS		0xffda0000
#define SOCFPGA_DMASECURE_ADDRESS		0xffda1000
#define SOCFPGA_MPUSCU_ADDRESS			0xffffc000
#define SOCFPGA_MPUL2_ADDRESS			0xfffff000
#define SOCFPGA_I2C0_ADDRESS			0xffc02200
#define SOCFPGA_I2C1_ADDRESS			0xffc02300
#define SOCFPGA_I2C2_ADDRESS			0xffc02400
#define SOCFPGA_I2C3_ADDRESS			0xffc02500
#define SOCFPGA_I2C4_ADDRESS			0xffc02600

#define SOCFPGA_ECC_OCRAM_ADDRESS		0xff8c3000
#define SOCFPGA_UART0_ADDRESS			0xffc02000
#define SOCFPGA_OSC1TIMER0_ADDRESS		0xffd00000
#define SOCFPGA_OSC1TIMER1_ADDRESS		0xffd00100
#define SOCFPGA_CLKMGR_ADDRESS			0xffd04000
#define SOCFPGA_RSTMGR_ADDRESS			0xffd05000

#define SOCFPGA_SDR_ADDRESS			0xffcfb000
#define SOCFPGA_NOC_L4_PRIV_FLT_OFST		0xffd11000
#define SOCFPGA_SDR_SCHEDULER_ADDRESS		0xffd12400
#define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS	0xffd13200
#define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS	0xffd13300
#define SOCFPGA_SDR_FIREWALL_L3_ADDRESS		0xffd13400
#define SOCFPGA_NOC_FW_H2F_SCR_OFST		0xffd13500

#define SOCFPGA_PHYS_OCRAM_SIZE			0x40000

#endif /* _SOCFPGA_A10_BASE_HARDWARE_H_ */
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> 2018-05-06 21:58:06 +00:00			`/* SPDX-License-Identifier: GPL-2.0+ */`
ARM: socfpga: arria10: add base address map for Arria10 Add the base address map for Arria10. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Reviewed-by: Marek Vasut <marex@denx.de> 2015-11-23 23:27:16 +00:00			`/*`
arm: socfpga: Add A10 macros Add i2c, timer and other A10 macros. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> 2017-04-25 18:44:37 +00:00			`* Copyright (C) 2014-2017 Altera Corporation <www.altera.com>`
ARM: socfpga: arria10: add base address map for Arria10 Add the base address map for Arria10. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Reviewed-by: Marek Vasut <marex@denx.de> 2015-11-23 23:27:16 +00:00			`*/`

			`#ifndef _SOCFPGA_A10_BASE_HARDWARE_H_`
			`#define _SOCFPGA_A10_BASE_HARDWARE_H_`

			`#define SOCFPGA_EMAC0_ADDRESS 0xff800000`
			`#define SOCFPGA_EMAC1_ADDRESS 0xff802000`
			`#define SOCFPGA_EMAC2_ADDRESS 0xff804000`
			`#define SOCFPGA_SDMMC_ADDRESS 0xff808000`
			`#define SOCFPGA_QSPIREGS_ADDRESS 0xff809000`
			`#define SOCFPGA_QSPIDATA_ADDRESS 0xffa00000`
			`#define SOCFPGA_UART1_ADDRESS 0xffc02100`
			`#define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xffcfa000`
			`#define SOCFPGA_FPGAMGRDATA_ADDRESS 0xffcfe400`
			`#define SOCFPGA_FPGAMGRREGS_ADDRESS 0xffd03000`
			`#define SOCFPGA_L4WD0_ADDRESS 0xffd00200`
			`#define SOCFPGA_SYSMGR_ADDRESS 0xffd06000`
			`#define SOCFPGA_PINMUX_SHARED_3V_IO_ADDRESS 0xffd07000`
			`#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS 0xffd07200`
			`#define SOCFPGA_PINMUX_DEDICATED_IO_CFG_ADDRESS 0xffd07300`
			`#define SOCFPGA_PINMUX_FPGA_INTERFACE_ADDRESS 0xffd07400`
			`#define SOCFPGA_DMANONSECURE_ADDRESS 0xffda0000`
			`#define SOCFPGA_DMASECURE_ADDRESS 0xffda1000`
			`#define SOCFPGA_MPUSCU_ADDRESS 0xffffc000`
			`#define SOCFPGA_MPUL2_ADDRESS 0xfffff000`
			`#define SOCFPGA_I2C0_ADDRESS 0xffc02200`
			`#define SOCFPGA_I2C1_ADDRESS 0xffc02300`
arm: socfpga: Add A10 macros Add i2c, timer and other A10 macros. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> 2017-04-25 18:44:37 +00:00			`#define SOCFPGA_I2C2_ADDRESS 0xffc02400`
			`#define SOCFPGA_I2C3_ADDRESS 0xffc02500`
			`#define SOCFPGA_I2C4_ADDRESS 0xffc02600`
ARM: socfpga: arria10: add base address map for Arria10 Add the base address map for Arria10. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Reviewed-by: Marek Vasut <marex@denx.de> 2015-11-23 23:27:16 +00:00
			`#define SOCFPGA_ECC_OCRAM_ADDRESS 0xff8c3000`
			`#define SOCFPGA_UART0_ADDRESS 0xffc02000`
			`#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000`
arm: socfpga: Add A10 macros Add i2c, timer and other A10 macros. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> 2017-04-25 18:44:37 +00:00			`#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd00100`
ARM: socfpga: arria10: add base address map for Arria10 Add the base address map for Arria10. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Reviewed-by: Marek Vasut <marex@denx.de> 2015-11-23 23:27:16 +00:00			`#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000`
			`#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000`

			`#define SOCFPGA_SDR_ADDRESS 0xffcfb000`
arm: socfpga: Add A10 macros Add i2c, timer and other A10 macros. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> 2017-04-25 18:44:37 +00:00			`#define SOCFPGA_NOC_L4_PRIV_FLT_OFST 0xffd11000`
ARM: socfpga: arria10: add base address map for Arria10 Add the base address map for Arria10. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Reviewed-by: Marek Vasut <marex@denx.de> 2015-11-23 23:27:16 +00:00			`#define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xffd12400`
			`#define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS 0xffd13200`
			`#define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS 0xffd13300`
			`#define SOCFPGA_SDR_FIREWALL_L3_ADDRESS 0xffd13400`
arm: socfpga: Add A10 macros Add i2c, timer and other A10 macros. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> 2017-04-25 18:44:37 +00:00			`#define SOCFPGA_NOC_FW_H2F_SCR_OFST 0xffd13500`
ARM: socfpga: arria10: add base address map for Arria10 Add the base address map for Arria10. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Reviewed-by: Marek Vasut <marex@denx.de> 2015-11-23 23:27:16 +00:00
arm: socfpga: Add onchip RAM size macro Add OCRAM size macro for Gen5 and Arria 10. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> 2020-03-06 08:55:18 +00:00			`#define SOCFPGA_PHYS_OCRAM_SIZE 0x40000`

ARM: socfpga: arria10: add base address map for Arria10 Add the base address map for Arria10. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Reviewed-by: Marek Vasut <marex@denx.de> 2015-11-23 23:27:16 +00:00			`#endif /* _SOCFPGA_A10_BASE_HARDWARE_H_ */`