2012-12-23 19:25:27 +00:00
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Overview
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--------
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The B4860QDS is a Freescale reference board that hosts the B4860 SoC (and variants).
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B4860 Overview
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-------------
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The B4860 QorIQ Qonverge device is a Freescale high-end, multicore SoC based on
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2013-10-07 11:07:26 +00:00
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StarCore and Power Architecture® cores. It targets the broadband wireless
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2012-12-23 19:25:27 +00:00
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infrastructure and builds upon the proven success of the existing multicore
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DSPs and Power CPUs. It is designed to bolster the rapidly changing and
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expanding wireless markets, such as 3GLTE (FDD and TDD), LTE-Advanced, and UMTS.
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The B4860 is a highly-integrated StarCore and Power Architecture processor that
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contains:
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. Six fully-programmable StarCore SC3900 FVP subsystems, divided into three
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clusters-each core runs up to 1.2 GHz, with an architecture highly optimized for
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wireless base station applications
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. Four dual-thread e6500 Power Architecture processors organized in one cluster-each
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core runs up to 1.8 GHz
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. Two DDR3/3L controllers for high-speed, industry-standard memory interface each
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runs at up to 1866.67 MHz
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. MAPLE-B3 hardware acceleration-for forward error correction schemes including
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Turbo or Viterbi decoding, Turbo encoding and rate matching, MIMO MMSE
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equalization scheme, matrix operations, CRC insertion and check, DFT/iDFT and
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FFT/iFFT calculations, PUSCH/PDSCH acceleration, and UMTS chip rate
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acceleration
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. CoreNet fabric that fully supports coherency using MESI protocol between the
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e6500 cores, SC3900 FVP cores, memories and external interfaces.
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CoreNet fabric interconnect runs at 667 MHz and supports coherent and
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non-coherent out of order transactions with prioritization and bandwidth
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allocation amongst CoreNet endpoints.
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. Data Path Acceleration Architecture, which includes the following:
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. Frame Manager (FMan), which supports in-line packet parsing and general
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classification to enable policing and QoS-based packet distribution
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. Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading
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of queue management, task management, load distribution, flow ordering, buffer
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management, and allocation tasks from the cores
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. Security engine (SEC 5.3)-crypto-acceleration for protocols such as IPsec,
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SSL, and 802.16
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. RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and
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outbound). Supports types 5, 6 (outbound only)
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. Large internal cache memory with snooping and stashing capabilities for
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bandwidth saving and high utilization of processor elements. The 9856-Kbyte
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internal memory space includes the following:
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. 32 Kbyte L1 ICache per e6500/SC3900 core
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. 32 Kbyte L1 DCache per e6500/SC3900 core
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. 2048 Kbyte unified L2 cache for each SC3900 FVP cluster
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. 2048 Kbyte unified L2 cache for the e6500 cluster
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. Two 512 Kbyte shared L3 CoreNet platform caches (CPC)
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. Sixteen 10-GHz SerDes lanes serving:
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. Two Serial RapidIO interfaces.
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- Each supports up to 4 lanes and a total of up to 8 lanes
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. Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue-less
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antenna connection
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. Two 10-Gbit Ethernet controllers (10GEC)
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. Six 1G/2.5-Gbit Ethernet controllers for network communications
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. PCI Express controller
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. Debug (Aurora)
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. Two OCeaN DMAs
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. Various system peripherals
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. 182 32-bit timers
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B4860QDS Overview
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------------------
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- DDRC1: Ten separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s, ECC, 4 GB
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of memory in two ranks of 2 GB.
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- DDRC2: Five separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s, ECC, 2 GB
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of memory. Single rank.
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- SerDes 1 multiplexing: Two Vitesse (transmit and receive path) cross-point 16x16 switch
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VSC3316
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- SerDes 2 multiplexing: Two Vitesse (transmit and receive path) cross-point 8x8 switch VSC3308
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- USB 2.0 ULPI PHY USB3315 by SMSC supports USB port in host mode.
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B4860 UART port is available over USB-to-UART translator USB2SER or over RS232 flat cable.
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- A Vitesse dual SGMII phy VSC8662 links the B4860 SGMII lines to 2xRJ-45 copper connectors
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for Stand-alone mode and to the 1000Base-X over AMC MicroTCA connector ports 0 and 2 for
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AMC mode.
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- The B4860 configuration may be loaded from nine bits coded reset configuration reset source. The
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RCW source is set by appropriate DIP-switches:
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- 16-bit NOR Flash / PROMJet
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- QIXIS 8-bit NOR Flash Emulator
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- 8-bit NAND Flash
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- 24-bit SPI Flash
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- Long address I2C EEPROM
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- Available debug interfaces are:
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- On-board eCWTAP controller with ETH and USB I/F
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- JTAG/COP 16-pin header for any external TAP controller
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- External JTAG source over AMC to support B2B configuration
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- 70-pin Aurora debug connector
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- QIXIS (FPGA) logic:
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- 2 KB internal memory space including
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- IDT840NT4 clock synthesizer provides B4860 essential clocks : SYSCLK, DDRCLK1,2 and
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RTCCLK.
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- Two 8T49N222A SerDes ref clock devices support two SerDes port clock frequency - total four
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refclk, including CPRI clock scheme.
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B4420 Personality
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--------------------
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B4420 Personality
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--------------------
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B4420 is a reduced personality of B4860 with less core/clusters(both SC3900 and e6500), less DDR
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2013-10-07 11:07:26 +00:00
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controllers, less serdes lanes, less SGMII interfaces and reduced target frequencies.
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2012-12-23 19:25:27 +00:00
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Key differences between B4860 and B4420
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----------------------------------------
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2013-10-07 11:07:26 +00:00
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2012-12-23 19:25:27 +00:00
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B4420 has:
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1. Less e6500 cores: 1 cluster with 2 e6500 cores
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2. Less SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster.
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3. Single DDRC
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4. 2X 4 lane serdes
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5. 3 SGMII interfaces
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6. no sRIO
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7. no 10G
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B4860QDS Default Settings
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-------------------------
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Switch Settings
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----------------
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2015-05-14 11:17:16 +00:00
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SW1 OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0]
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2012-12-23 19:25:27 +00:00
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SW2 ON ON ON ON ON ON OFF OFF
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SW3 OFF OFF OFF ON OFF OFF ON OFF
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SW5 OFF OFF OFF OFF OFF OFF ON ON
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Note: PCIe slots modes: All the PCIe devices work as Root Complex.
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Note: Boot location: NOR flash.
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SysClk/Core(e6500)/CCB/DDR/FMan/DDRCLK/StarCore/CPRI-Maple/eTVPE-Maple/ULB-Maple
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66MHz/1.6GHz/667MHz/1.6GHz data rate/667MHz/133MHz/1200MHz/500MHz/800MHz/667MHz
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2013-10-07 11:07:26 +00:00
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a) NAND boot
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2012-12-23 19:25:27 +00:00
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SW1 [1.1] = 0
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SW2 [1.1] = 1
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SW3 [1:4] = 0001
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b) NOR boot
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SW1 [1.1] = 1
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SW2 [1.1] = 0
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SW3 [1:4] = 1000.
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B4420QDS Default Settings
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-------------------------
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Switch Settings
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----------------
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SW1 OFF[0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0]
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SW2 ON OFF ON OFF ON ON OFF OFF
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SW3 OFF OFF OFF ON OFF OFF ON OFF
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SW5 OFF OFF OFF OFF OFF OFF ON ON
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Note: PCIe slots modes: All the PCIe devices work as Root Complex.
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Note: Boot location: NOR flash.
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SysClk/Core(e6500)/CCB/DDR/FMan/DDRCLK/StarCore/CPRI-Maple/eTVPE-Maple/ULB-Maple
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66MHz/1.6GHz/667MHz/1.6GHz data rate/667MHz/133MHz/1200MHz/500MHz/800MHz/667MHz
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2013-10-07 11:07:26 +00:00
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a) NAND boot
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2012-12-23 19:25:27 +00:00
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SW1 [1.1] = 0
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SW2 [1.1] = 1
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SW3 [1:4] = 0001
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b) NOR boot
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SW1 [1.1] = 1
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SW2 [1.1] = 0
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SW3 [1:4] = 1000.
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Memory map on B4860QDS
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----------------------
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The addresses in brackets are physical addresses.
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Start Address End Address Description Size
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0xF_FFDF_1000 0xF_FFFF_FFFF Free 2 MB
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0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4 KB
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0xF_FF81_0000 0xF_FFDE_FFFF Free 5 MB
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0xF_FF80_0000 0xF_FF80_FFFF IFC NAND Flash 64 KB
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0xF_FF00_0000 0xF_FF7F_FFFF Free 8 MB
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0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16 MB
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0xF_F801_0000 0xF_FDFF_FFFF Free 95 MB
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0xF_F800_0000 0xF_F800_FFFF PCIe I/O Space 64 KB
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0xF_F600_0000 0xF_F7FF_FFFF QMAN s/w portal 32 MB
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0xF_F400_0000 0xF_F5FF_FFFF BMAN s/w portal 32 MB
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0xF_F000_0000 0xF_F3FF_FFFF Free 64 MB
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0xF_E800_0000 0xF_EFFF_FFFF IFC NOR Flash 128 MB
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0xF_E000_0000 0xF_E7FF_FFFF Promjet 128 MB
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0xF_A0C0_0000 0xF_DFFF_FFFF Free 1012 MB
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0xF_A000_0000 0xF_A0BF_FFFF MAPLE0/1/2 12 MB
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0xF_0040_0000 0xF_9FFF_FFFF Free 12 GB
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2013-03-25 07:40:12 +00:00
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0xF_0000_0000 0xF_01FF_FFFF DCSR 32 MB
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2012-12-23 19:25:27 +00:00
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0xC_4000_0000 0xE_FFFF_FFFF Free 11 GB
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0xC_3000_0000 0xC_3FFF_FFFF sRIO-2 I/O 256 MB
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0xC_2000_0000 0xC_2FFF_FFFF sRIO-1 I/O 256 MB
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0xC_0000_0000 0xC_1FFF_FFFF PCIe Mem Space 512 MB
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0x1_0000_0000 0xB_FFFF_FFFF Free 44 GB
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0x0_8000_0000 0x0_FFFF_FFFF DDRC1 2 GB
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0x0_0000_0000 0x0_7FFF_FFFF DDRC2 2 GB
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Memory map on B4420QDS
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----------------------
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The addresses in brackets are physical addresses.
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Start Address End Address Description Size
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0xF_FFDF_1000 0xF_FFFF_FFFF Free 2 MB
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0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4 KB
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0xF_FF81_0000 0xF_FFDE_FFFF Free 5 MB
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0xF_FF80_0000 0xF_FF80_FFFF IFC NAND Flash 64 KB
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0xF_FF00_0000 0xF_FF7F_FFFF Free 8 MB
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0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16 MB
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0xF_F801_0000 0xF_FDFF_FFFF Free 95 MB
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0xF_F800_0000 0xF_F800_FFFF PCIe I/O Space 64 KB
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0xF_F600_0000 0xF_F7FF_FFFF QMAN s/w portal 32 MB
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0xF_F400_0000 0xF_F5FF_FFFF BMAN s/w portal 32 MB
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0xF_F000_0000 0xF_F3FF_FFFF Free 64 MB
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0xF_E800_0000 0xF_EFFF_FFFF IFC NOR Flash 128 MB
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0xF_E000_0000 0xF_E7FF_FFFF Promjet 128 MB
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0xF_A0C0_0000 0xF_DFFF_FFFF Free 1012 MB
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0xF_A000_0000 0xF_A0BF_FFFF MAPLE0/1/2 12 MB
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0xF_0040_0000 0xF_9FFF_FFFF Free 12 GB
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2013-03-25 07:40:12 +00:00
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0xF_0000_0000 0xF_01FF_FFFF DCSR 32 MB
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2012-12-23 19:25:27 +00:00
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0xC_4000_0000 0xE_FFFF_FFFF Free 11 GB
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0xC_3000_0000 0xC_3FFF_FFFF sRIO-2 I/O 256 MB
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0xC_2000_0000 0xC_2FFF_FFFF sRIO-1 I/O 256 MB
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0xC_0000_0000 0xC_1FFF_FFFF PCIe Mem Space 512 MB
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0x1_0000_0000 0xB_FFFF_FFFF Free 44 GB
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0x0_0000_0000 0x0_FFFF_FFFF DDRC1 4 GB
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NOR Flash memory Map on B4860 and B4420QDS
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------------------------------------------
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Start End Definition Size
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2016-02-06 03:30:11 +00:00
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0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB
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0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB
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2014-01-14 06:04:26 +00:00
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0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
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2014-01-25 06:41:23 +00:00
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0xEF300000 0xEFEFFFFF rootfs (alternate bank) 12MB
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2012-12-23 19:25:27 +00:00
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0xEE800000 0xEE8FFFFF device tree (alternate bank) 1MB
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0xEE020000 0xEE6FFFFF Linux.uImage (alternate bank) 6MB+896KB
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0xEE000000 0xEE01FFFF RCW (alternate bank) 128KB
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2016-02-06 03:30:11 +00:00
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0xEDF40000 0xEDFFFFFF U-Boot (alternate bank) 768KB
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0xEDF20000 0xEDF3FFFF U-Boot env (alternate bank) 128KB
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2014-01-14 06:04:26 +00:00
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0xEDF00000 0xEDF1FFFF FMAN ucode (alternate bank) 128KB
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2014-01-25 06:41:23 +00:00
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0xED300000 0xEDEFFFFF rootfs (current bank) 12MB
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2012-12-23 19:25:27 +00:00
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0xEC800000 0xEC8FFFFF device tree (current bank) 1MB
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0xEC020000 0xEC6FFFFF Linux.uImage (current bank) 6MB+896KB
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0xEC000000 0xEC01FFFF RCW (current bank) 128KB
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Various Software configurations/environment variables/commands
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--------------------------------------------------------------
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The below commands apply to both B4860QDS and B4420QDS.
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2016-02-06 03:30:11 +00:00
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1. U-Boot environment variable hwconfig
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2012-12-23 19:25:27 +00:00
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The default hwconfig is:
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hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1:
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dr_mode=host,phy_type=ulpi
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Note: For USB gadget set "dr_mode=peripheral"
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2. FMAN Ucode versions
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fsl_fman_ucode_B4860_106_3_6.bin
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3. Switching to alternate bank
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Commands for switching to alternate bank.
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2013-10-07 11:07:26 +00:00
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1. To change from vbank0 to vbank2
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2012-12-23 19:25:27 +00:00
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=> qixis_reset altbank (it will boot using vbank2)
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2.To change from vbank2 to vbank0
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=> qixis reset (it will boot using vbank0)
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4. To change personality of board
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For changing personality from B4860 to B4420
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1)Boot from vbank0
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2016-02-06 03:30:11 +00:00
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2)Flash vbank2 with b4420 rcw and U-Boot
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2012-12-23 19:25:27 +00:00
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3)Give following commands to uboot prompt
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2013-10-07 11:07:26 +00:00
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=> mw.b ffdf0040 0x30;
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2012-12-23 19:25:27 +00:00
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=> mw.b ffdf0010 0x00;
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=> mw.b ffdf0062 0x02;
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=> mw.b ffdf0050 0x02;
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=> mw.b ffdf0010 0x30;
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=> reset
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Note: Power off cycle will lead to default switch settings.
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Note: 0xffdf0000 is the address of the QIXIS FPGA.
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5. Switching between NOR and NAND boot(RCW src changed from NOR <-> NAND)
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To change from NOR to NAND boot give following command on uboot prompt
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=> mw.b ffdf0040 0x30
|
2013-10-07 11:07:26 +00:00
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=> mw.b ffdf0010 0x00
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2012-12-23 19:25:27 +00:00
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=> mw.b 0xffdf0050 0x08
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=> mw.b 0xffdf0060 0x82
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=> mw.b ffdf0061 0x00
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2013-10-07 11:07:26 +00:00
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=> mw.b ffdf0010 0x30
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2012-12-23 19:25:27 +00:00
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=> reset
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To change from NAND to NOR boot give following command on uboot prompt:
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=> mw.b ffdf0040 0x30
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2013-10-07 11:07:26 +00:00
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=> mw.b ffdf0010 0x00
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2012-12-23 19:25:27 +00:00
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=> mw.b 0xffdf0050 0x00(for vbank0) or (mw.b 0xffdf0050 0x02 for vbank2)
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=> mw.b 0xffdf0060 0x12
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=> mw.b ffdf0061 0x01
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2013-10-07 11:07:26 +00:00
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=> mw.b ffdf0010 0x30
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2012-12-23 19:25:27 +00:00
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=> reset
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Note: Power off cycle will lead to default switch settings.
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Note: 0xffdf0000 is the address of the QIXIS FPGA.
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|
2013-10-07 11:07:26 +00:00
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6. Ethernet interfaces for B4860QDS
|
2012-12-23 19:25:27 +00:00
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Serdes protocosl tested:
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0x2a, 0x8d (serdes1, serdes2) [DEFAULT]
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0x2a, 0xb2 (serdes1, serdes2)
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When using [DEFAULT] RCW, which including 2 * 1G SGMII on board and 2 * 1G
|
2013-10-07 11:07:26 +00:00
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SGMII on SGMII riser card.
|
2016-02-06 03:30:11 +00:00
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Under U-Boot these network interfaces are recognized as:
|
2012-12-23 19:25:27 +00:00
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FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5 and FM1@DTSEC6.
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On Linux the interfaces are renamed as:
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. eth2 -> fm1-gb2
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. eth3 -> fm1-gb3
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. eth4 -> fm1-gb4
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. eth5 -> fm1-gb5
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|
2013-10-07 11:07:26 +00:00
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|
7. RCW and Ethernet interfaces for B4420QDS
|
2012-12-23 19:25:27 +00:00
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|
|
Serdes protocosl tested:
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0x18, 0x9e (serdes1, serdes2)
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|
2016-02-06 03:30:11 +00:00
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|
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Under U-Boot these network interfaces are recognized as:
|
2012-12-23 19:25:27 +00:00
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FM1@DTSEC3, FM1@DTSEC4 and e1000#0.
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On Linux the interfaces are renamed as:
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. eth2 -> fm1-gb2
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. eth3 -> fm1-gb3
|
2014-04-08 13:43:44 +00:00
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NAND boot with 2 Stage boot loader
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----------------------------------
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PBL initialise the internal SRAM and copy SPL(160KB) in SRAM.
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SPL further initialise DDR using SPD and environment variables and copy
|
2016-02-06 03:30:11 +00:00
|
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|
U-Boot(768 KB) from flash to DDR.
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|
|
Finally SPL transer control to U-Boot for futher booting.
|
2014-04-08 13:43:44 +00:00
|
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SPL has following features:
|
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|
|
- Executes within 256K
|
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- No relocation required
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Run time view of SPL framework during boot :-
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-----------------------------------------------
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Area | Address |
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-----------------------------------------------
|
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Secure boot | 0xFFFC0000 (32KB) |
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headers | |
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|
-----------------------------------------------
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GD, BD | 0xFFFC8000 (4KB) |
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-----------------------------------------------
|
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|
ENV | 0xFFFC9000 (8KB) |
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-----------------------------------------------
|
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|
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HEAP | 0xFFFCB000 (30KB) |
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-----------------------------------------------
|
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|
|
STACK | 0xFFFD8000 (22KB) |
|
|
|
|
|
-----------------------------------------------
|
2016-02-06 03:30:11 +00:00
|
|
|
U-Boot SPL | 0xFFFD8000 (160KB) |
|
2014-04-08 13:43:44 +00:00
|
|
|
-----------------------------------------------
|
|
|
|
|
|
|
|
|
|
NAND Flash memory Map on B4860 and B4420QDS
|
|
|
|
|
------------------------------------------
|
|
|
|
|
Start End Definition Size
|
2016-02-06 03:30:11 +00:00
|
|
|
0x000000 0x0FFFFF U-Boot 1MB
|
|
|
|
|
0x140000 0x15FFFF U-Boot env 128KB
|
2014-04-08 13:43:44 +00:00
|
|
|
0x1A0000 0x1BFFFF FMAN Ucode 128KB
|
