u-boot/arch/arm/include/asm/arch-aspeed/platform.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) ASPEED Technology Inc.
 * Ryan Chen <ryan_chen@aspeedtech.com>
 *
 */

#ifndef _ASM_ARCH_PLATFORM_H
#define _ASM_ARCH_PLATFORM_H

#if defined(CONFIG_ASPEED_AST2500)
#define ASPEED_MAC_COUNT	2
#define ASPEED_DRAM_BASE	0x80000000
#define ASPEED_SRAM_BASE	0x1e720000
#define ASPEED_SRAM_SIZE	0x9000
#elif defined(CONFIG_ASPEED_AST2600)
#define ASPEED_MAC_COUNT	4
#define ASPEED_DRAM_BASE	0x80000000
#define ASPEED_SRAM_BASE	0x10000000
#define ASPEED_SRAM_SIZE	0x16000
#else
#err "Unrecognized Aspeed platform."
#endif

#endif
include/configs: aspeed: Remove hardcoded variables The hardcoded platform variables such as DRAM base address are not common to Aspeed SoCs AST24xx/AST25xx/AST26xx. This patch replaces those hardcoded with macros defined in a newly added header, where the basic SoC HW information are assigned accordingly. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> 2020-08-03 09:36:08 +00:00			`/* SPDX-License-Identifier: GPL-2.0+ */`
			`/*`
			`* Copyright (C) ASPEED Technology Inc.`
			`* Ryan Chen <ryan_chen@aspeedtech.com>`
			`*`
			`*/`

			`#ifndef _ASM_ARCH_PLATFORM_H`
			`#define _ASM_ARCH_PLATFORM_H`

			`#if defined(CONFIG_ASPEED_AST2500)`
			`#define ASPEED_MAC_COUNT 2`
			`#define ASPEED_DRAM_BASE 0x80000000`
			`#define ASPEED_SRAM_BASE 0x1e720000`
			`#define ASPEED_SRAM_SIZE 0x9000`
aspeed: Add AST2600 platform support Add low level platform initialization for the AST2600 SoC. The 2-stage booting with U-Boot SPL are leveraged to support different booting mode. However, currently the patch supports only the booting from memory-mapped SPI flash. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com> 2020-12-14 05:54:28 +00:00			`#elif defined(CONFIG_ASPEED_AST2600)`
			`#define ASPEED_MAC_COUNT 4`
			`#define ASPEED_DRAM_BASE 0x80000000`
			`#define ASPEED_SRAM_BASE 0x10000000`
aspeed: ast2600: Enlarge SRAM size The AST2600 SRAM has been extended to 88KB since A1 chip revision. This patch updates the SRAM size to offer more space for early stack/heap use. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au> 2021-10-27 06:17:25 +00:00			`#define ASPEED_SRAM_SIZE 0x16000`
include/configs: aspeed: Remove hardcoded variables The hardcoded platform variables such as DRAM base address are not common to Aspeed SoCs AST24xx/AST25xx/AST26xx. This patch replaces those hardcoded with macros defined in a newly added header, where the basic SoC HW information are assigned accordingly. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> 2020-08-03 09:36:08 +00:00			`#else`
			`#err "Unrecognized Aspeed platform."`
			`#endif`

			`#endif`