2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2011-11-01 20:00:31 +00:00
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/*
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* Copyright (C) 2011
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*/
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#ifndef _DV_SYSCFG_DEFS_H_
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#define _DV_SYSCFG_DEFS_H_
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#ifndef CONFIG_SOC_DA8XX
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/* System Control Module register structure for DM365 */
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struct dv_sys_module_regs {
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unsigned int pinmux[5]; /* 0x00 */
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unsigned int bootcfg; /* 0x14 */
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unsigned int arm_intmux; /* 0x18 */
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unsigned int edma_evtmux; /* 0x1C */
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unsigned int ddr_slew; /* 0x20 */
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unsigned int clkout; /* 0x24 */
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unsigned int device_id; /* 0x28 */
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unsigned int vdac_config; /* 0x2C */
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unsigned int timer64_ctl; /* 0x30 */
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unsigned int usbbphy_ctl; /* 0x34 */
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unsigned int misc; /* 0x38 */
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unsigned int mstpri[2]; /* 0x3C */
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unsigned int vpss_clkctl; /* 0x44 */
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unsigned int peri_clkctl; /* 0x48 */
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unsigned int deepsleep; /* 0x4C */
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unsigned int dft_enable; /* 0x50 */
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unsigned int debounce[8]; /* 0x54 */
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unsigned int vtpiocr; /* 0x74 */
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unsigned int pupdctl0; /* 0x78 */
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unsigned int pupdctl1; /* 0x7C */
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unsigned int hdimcopbt; /* 0x80 */
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unsigned int pll0_config; /* 0x84 */
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unsigned int pll1_config; /* 0x88 */
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};
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#define VPTIO_RDY (1 << 15)
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#define VPTIO_IOPWRDN (1 << 14)
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#define VPTIO_CLRZ (1 << 13)
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#define VPTIO_LOCK (1 << 7)
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#define VPTIO_PWRDN (1 << 6)
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#define VPSS_CLK_CTL_VPSS_CLKMD (1 << 7)
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#define dv_sys_module_regs \
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((struct dv_sys_module_regs *)DAVINCI_SYSTEM_MODULE_BASE)
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#endif /* !CONFIG_SOC_DA8XX */
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#endif /* _DV_SYSCFG_DEFS_H_ */
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