2018-05-06 17:58:06 -04:00
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// SPDX-License-Identifier: GPL-2.0+
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2012-06-13 16:29:47 +09:00
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/*
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* (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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2021-03-17 14:11:50 +00:00
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* (C) Copyright 2012-2021 Renesas Solutions Corp.
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2012-06-13 16:29:47 +09:00
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*/
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#include <common.h>
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2019-11-14 12:57:37 -07:00
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#include <cpu_func.h>
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2020-05-10 11:39:56 -06:00
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#include <asm/cache.h>
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2020-05-10 11:40:02 -06:00
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#include <init.h>
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2012-06-13 16:29:47 +09:00
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#include <asm/io.h>
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2019-08-01 09:46:51 -06:00
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#include <env.h>
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2018-12-03 13:28:25 +01:00
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#include <linux/ctype.h>
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2012-06-13 16:29:47 +09:00
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#ifdef CONFIG_ARCH_CPU_INIT
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int arch_cpu_init(void)
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{
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icache_enable();
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return 0;
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}
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#endif
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2023-02-28 22:22:03 +01:00
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/* R-Car Gen3 and Gen4 D-cache is enabled in memmap-gen3.c */
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#ifndef CONFIG_RCAR_64
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2019-05-03 09:41:00 -04:00
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#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
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2012-06-13 16:29:47 +09:00
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void enable_caches(void)
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{
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dcache_enable();
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}
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#endif
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2018-10-31 15:06:50 +01:00
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#endif
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2012-06-13 16:29:47 +09:00
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#ifdef CONFIG_DISPLAY_CPUINFO
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ARM: rmobile: Add support for Renesas RZ/N1 SoC
The RZ/N1 is a family of SoC devices from Renesas, featuring:
* ARM Cortex-A7 CPU (single/dual core) and/or Cortex-M3
* Integrated SRAM up to 6MB
* Integrated gigabit ethernet switch
* Optional DDR2/3 controller
* I2C, SPI, UART, NAND, QSPI, SDIO, USB, CAN, RTC, LCD
Add basic support for this family, modeled on the existing RZA1.
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-05-12 21:36:55 -04:00
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#if !defined(CONFIG_RZA1) && !defined(CONFIG_RZN1)
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2021-03-17 14:11:50 +00:00
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__weak const u8 *rzg_get_cpu_name(void)
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{
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return 0;
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}
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2012-08-19 04:40:05 +00:00
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static u32 __rmobile_get_cpu_type(void)
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2012-06-13 16:29:47 +09:00
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{
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2012-08-19 04:40:05 +00:00
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return 0x0;
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2012-06-13 16:29:47 +09:00
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}
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2012-08-19 04:40:05 +00:00
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u32 rmobile_get_cpu_type(void)
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__attribute__((weak, alias("__rmobile_get_cpu_type")));
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2012-06-13 16:29:47 +09:00
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2012-07-25 18:24:21 +00:00
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static u32 __rmobile_get_cpu_rev_integer(void)
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2012-06-13 16:29:47 +09:00
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{
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2012-08-19 04:40:05 +00:00
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return 0;
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2012-06-13 16:29:47 +09:00
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}
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2012-07-25 18:24:21 +00:00
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u32 rmobile_get_cpu_rev_integer(void)
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__attribute__((weak, alias("__rmobile_get_cpu_rev_integer")));
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static u32 __rmobile_get_cpu_rev_fraction(void)
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{
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return 0;
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}
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u32 rmobile_get_cpu_rev_fraction(void)
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__attribute__((weak, alias("__rmobile_get_cpu_rev_fraction")));
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2012-06-13 16:29:47 +09:00
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2021-03-17 14:11:50 +00:00
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/* CPU information table */
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2014-03-28 11:54:22 +09:00
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static const struct {
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u16 cpu_type;
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u8 cpu_name[10];
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} rmobile_cpuinfo[] = {
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2017-11-25 23:54:10 +01:00
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{ RMOBILE_CPU_TYPE_R8A7740, "R8A7740" },
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{ RMOBILE_CPU_TYPE_R8A7790, "R8A7790" },
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{ RMOBILE_CPU_TYPE_R8A7791, "R8A7791" },
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{ RMOBILE_CPU_TYPE_R8A7792, "R8A7792" },
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{ RMOBILE_CPU_TYPE_R8A7793, "R8A7793" },
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{ RMOBILE_CPU_TYPE_R8A7794, "R8A7794" },
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{ RMOBILE_CPU_TYPE_R8A7795, "R8A7795" },
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{ RMOBILE_CPU_TYPE_R8A7796, "R8A7796" },
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2018-02-26 10:35:15 +01:00
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{ RMOBILE_CPU_TYPE_R8A77965, "R8A77965" },
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2017-10-09 20:39:47 +02:00
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{ RMOBILE_CPU_TYPE_R8A77970, "R8A77970" },
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2019-07-29 19:59:44 +02:00
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{ RMOBILE_CPU_TYPE_R8A77980, "R8A77980" },
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2018-04-26 10:09:06 +02:00
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{ RMOBILE_CPU_TYPE_R8A77990, "R8A77990" },
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2017-10-08 20:52:52 +02:00
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{ RMOBILE_CPU_TYPE_R8A77995, "R8A77995" },
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2020-05-21 14:11:13 +07:00
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{ RMOBILE_CPU_TYPE_R8A779A0, "R8A779A0" },
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2023-02-28 22:34:45 +01:00
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{ RMOBILE_CPU_TYPE_R8A779F0, "R8A779F0" },
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2023-02-28 22:37:07 +01:00
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{ RMOBILE_CPU_TYPE_R8A779G0, "R8A779G0" },
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2014-03-28 11:54:22 +09:00
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{ 0x0, "CPU" },
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};
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2018-12-03 13:28:25 +01:00
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static int rmobile_cpuinfo_idx(void)
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2012-06-13 16:29:47 +09:00
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{
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2014-03-28 11:54:22 +09:00
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int i = 0;
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u32 cpu_type = rmobile_get_cpu_type();
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2018-12-03 13:28:25 +01:00
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for (; i < ARRAY_SIZE(rmobile_cpuinfo); i++)
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if (rmobile_cpuinfo[i].cpu_type == cpu_type)
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2014-03-28 11:54:22 +09:00
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break;
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2018-12-03 13:28:25 +01:00
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return i;
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}
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2021-03-17 14:11:50 +00:00
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static const u8 *get_cpu_name(int idx)
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{
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const u8 *cpu_name = rzg_get_cpu_name();
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return cpu_name ? cpu_name : rmobile_cpuinfo[idx].cpu_name;
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}
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2018-12-03 13:28:25 +01:00
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#ifdef CONFIG_ARCH_MISC_INIT
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int arch_misc_init(void)
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{
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int i, idx = rmobile_cpuinfo_idx();
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2021-03-17 14:11:50 +00:00
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const u8 *cpu_name = get_cpu_name(idx);
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2018-12-03 13:28:25 +01:00
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char cpu[10] = { 0 };
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for (i = 0; i < sizeof(cpu); i++)
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2021-03-17 14:11:50 +00:00
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cpu[i] = tolower(cpu_name[i]);
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2018-12-03 13:28:25 +01:00
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env_set("platform", cpu);
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return 0;
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}
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#endif
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int print_cpuinfo(void)
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{
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int i = rmobile_cpuinfo_idx();
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2018-09-26 18:14:41 +09:00
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if (rmobile_cpuinfo[i].cpu_type == RMOBILE_CPU_TYPE_R8A7796 &&
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rmobile_get_cpu_rev_integer() == 1 &&
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rmobile_get_cpu_rev_fraction() == 1) {
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printf("CPU: Renesas Electronics %s rev 1.1/1.2\n", get_cpu_name(i));
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return 0;
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}
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2021-07-04 17:27:27 +02:00
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printf("CPU: Renesas Electronics %s rev %d.%d\n",
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2021-03-17 14:11:50 +00:00
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get_cpu_name(i), rmobile_get_cpu_rev_integer(),
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2018-12-03 13:28:25 +01:00
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rmobile_get_cpu_rev_fraction());
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2012-06-13 16:29:47 +09:00
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return 0;
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}
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ARM: rmobile: Add support for Renesas RZ/N1 SoC
The RZ/N1 is a family of SoC devices from Renesas, featuring:
* ARM Cortex-A7 CPU (single/dual core) and/or Cortex-M3
* Integrated SRAM up to 6MB
* Integrated gigabit ethernet switch
* Optional DDR2/3 controller
* I2C, SPI, UART, NAND, QSPI, SDIO, USB, CAN, RTC, LCD
Add basic support for this family, modeled on the existing RZA1.
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-05-12 21:36:55 -04:00
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#elif defined(CONFIG_RZA1)
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2017-08-23 14:53:59 -05:00
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int print_cpuinfo(void)
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{
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printf("CPU: Renesas Electronics RZ/A1\n");
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return 0;
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}
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ARM: rmobile: Add support for Renesas RZ/N1 SoC
The RZ/N1 is a family of SoC devices from Renesas, featuring:
* ARM Cortex-A7 CPU (single/dual core) and/or Cortex-M3
* Integrated SRAM up to 6MB
* Integrated gigabit ethernet switch
* Optional DDR2/3 controller
* I2C, SPI, UART, NAND, QSPI, SDIO, USB, CAN, RTC, LCD
Add basic support for this family, modeled on the existing RZA1.
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-05-12 21:36:55 -04:00
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#else /* CONFIG_RZN1 */
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int print_cpuinfo(void)
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{
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printf("CPU: Renesas Electronics RZ/N1\n");
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return 0;
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}
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2017-08-23 14:53:59 -05:00
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#endif
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2012-08-19 04:40:05 +00:00
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#endif /* CONFIG_DISPLAY_CPUINFO */
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