2014-11-26 09:33:59 +00:00
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/*
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2016-10-07 07:43:00 +00:00
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* Device Tree Source for UniPhier sLD8 SoC
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2014-11-26 09:33:59 +00:00
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*
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2016-10-07 07:43:00 +00:00
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* Copyright (C) 2015-2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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2014-11-26 09:33:59 +00:00
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*
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2017-06-22 07:46:40 +00:00
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* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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2014-11-26 09:33:59 +00:00
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*/
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/ {
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2016-10-07 07:43:00 +00:00
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compatible = "socionext,uniphier-sld8";
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2017-03-12 15:16:39 +00:00
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#address-cells = <1>;
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#size-cells = <1>;
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2014-11-26 09:33:59 +00:00
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cpus {
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#address-cells = <1>;
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2014-12-05 15:03:23 +00:00
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#size-cells = <0>;
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2014-11-26 09:33:59 +00:00
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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2016-10-07 07:43:00 +00:00
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enable-method = "psci";
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2015-12-16 01:54:08 +00:00
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next-level-cache = <&l2>;
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2014-11-26 09:33:59 +00:00
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};
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};
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2016-12-05 09:31:39 +00:00
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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2015-06-30 09:27:00 +00:00
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clocks {
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2016-12-05 09:31:39 +00:00
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refclk: ref {
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2015-06-30 09:27:00 +00:00
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compatible = "fixed-clock";
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2016-12-05 09:31:39 +00:00
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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2015-06-30 09:27:00 +00:00
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};
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2015-08-28 13:33:13 +00:00
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2016-12-05 09:31:39 +00:00
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arm_timer_clk: arm_timer_clk {
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2015-08-28 13:33:13 +00:00
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#clock-cells = <0>;
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compatible = "fixed-clock";
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2016-12-05 09:31:39 +00:00
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clock-frequency = <50000000>;
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2015-08-28 13:33:13 +00:00
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};
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2015-06-30 09:27:00 +00:00
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};
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2016-12-05 09:31:39 +00:00
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupt-parent = <&intc>;
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u-boot,dm-pre-reloc;
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l2: l2-cache@500c0000 {
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compatible = "socionext,uniphier-system-cache";
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reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
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<0x506c0000 0x400>;
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interrupts = <0 174 4>, <0 175 4>;
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cache-unified;
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cache-size = <(256 * 1024)>;
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cache-sets = <256>;
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cache-line-size = <128>;
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cache-level = <2>;
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};
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2015-12-16 01:54:08 +00:00
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2016-12-05 09:31:39 +00:00
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serial0: serial@54006800 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006800 0x40>;
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interrupts = <0 33 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart0>;
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clocks = <&peri_clk 0>;
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clock-frequency = <80000000>;
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};
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2016-02-16 08:03:51 +00:00
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2016-12-05 09:31:39 +00:00
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serial1: serial@54006900 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006900 0x40>;
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interrupts = <0 35 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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clocks = <&peri_clk 1>;
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clock-frequency = <80000000>;
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};
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2016-02-16 08:03:51 +00:00
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2016-12-05 09:31:39 +00:00
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serial2: serial@54006a00 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006a00 0x40>;
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interrupts = <0 37 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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clocks = <&peri_clk 2>;
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clock-frequency = <80000000>;
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};
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2016-02-16 08:03:51 +00:00
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2016-12-05 09:31:39 +00:00
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serial3: serial@54006b00 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006b00 0x40>;
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interrupts = <0 29 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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clocks = <&peri_clk 3>;
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clock-frequency = <80000000>;
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};
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2016-02-16 08:03:51 +00:00
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2016-12-05 09:31:39 +00:00
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port0x: gpio@55000008 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000008 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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2016-02-16 08:03:51 +00:00
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2016-12-05 09:31:39 +00:00
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port1x: gpio@55000010 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000010 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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2016-02-16 08:03:51 +00:00
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2016-12-05 09:31:39 +00:00
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port2x: gpio@55000018 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000018 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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2016-02-16 08:03:51 +00:00
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2016-12-05 09:31:39 +00:00
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port3x: gpio@55000020 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000020 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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2016-02-16 08:03:51 +00:00
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2016-12-05 09:31:39 +00:00
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port4: gpio@55000028 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000028 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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2016-02-16 08:03:51 +00:00
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2016-12-05 09:31:39 +00:00
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port5x: gpio@55000030 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000030 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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2016-02-16 08:03:51 +00:00
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2016-12-05 09:31:39 +00:00
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port6x: gpio@55000038 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000038 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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2016-02-16 08:03:51 +00:00
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2016-12-05 09:31:39 +00:00
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port7x: gpio@55000040 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000040 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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2016-02-16 08:03:51 +00:00
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2016-12-05 09:31:39 +00:00
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port8x: gpio@55000048 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000048 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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2016-02-16 08:03:51 +00:00
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2016-12-05 09:31:39 +00:00
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port9x: gpio@55000050 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000050 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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2016-02-16 08:03:51 +00:00
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2016-12-05 09:31:39 +00:00
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port10x: gpio@55000058 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000058 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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2016-02-16 08:03:51 +00:00
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2016-12-05 09:31:39 +00:00
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port11x: gpio@55000060 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000060 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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2016-02-16 08:03:51 +00:00
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2016-12-05 09:31:39 +00:00
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port12x: gpio@55000068 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000068 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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2014-12-05 15:03:23 +00:00
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2016-12-05 09:31:39 +00:00
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port13x: gpio@55000070 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000070 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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2014-12-05 15:03:23 +00:00
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2016-12-05 09:31:39 +00:00
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port14x: gpio@55000078 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000078 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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2015-06-30 09:27:00 +00:00
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2016-12-05 09:31:39 +00:00
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port16x: gpio@55000088 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000088 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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2014-11-26 09:34:01 +00:00
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2016-12-05 09:31:39 +00:00
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i2c0: i2c@58400000 {
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compatible = "socionext,uniphier-i2c";
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status = "disabled";
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reg = <0x58400000 0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 41 1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c0>;
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clocks = <&peri_clk 4>;
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clock-frequency = <100000>;
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};
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2016-02-18 10:52:50 +00:00
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2016-12-05 09:31:39 +00:00
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i2c1: i2c@58480000 {
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compatible = "socionext,uniphier-i2c";
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status = "disabled";
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reg = <0x58480000 0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 42 1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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clocks = <&peri_clk 5>;
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clock-frequency = <100000>;
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};
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2016-02-18 10:52:50 +00:00
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2016-12-05 09:31:39 +00:00
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/* chip-internal connection for DMD */
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i2c2: i2c@58500000 {
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compatible = "socionext,uniphier-i2c";
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reg = <0x58500000 0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 43 1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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clocks = <&peri_clk 6>;
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clock-frequency = <400000>;
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};
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2014-11-26 09:34:01 +00:00
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2016-12-05 09:31:39 +00:00
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i2c3: i2c@58580000 {
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compatible = "socionext,uniphier-i2c";
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status = "disabled";
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reg = <0x58580000 0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 44 1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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clocks = <&peri_clk 7>;
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clock-frequency = <100000>;
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};
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2015-08-28 13:33:13 +00:00
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2016-12-05 09:31:39 +00:00
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system_bus: system-bus@58c00000 {
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compatible = "socionext,uniphier-system-bus";
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status = "disabled";
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reg = <0x58c00000 0x400>;
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#address-cells = <2>;
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#size-cells = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_system_bus>;
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};
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2016-06-29 10:39:02 +00:00
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2017-05-15 05:23:46 +00:00
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smpctrl@59801000 {
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2016-12-05 09:31:39 +00:00
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compatible = "socionext,uniphier-smpctrl";
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reg = <0x59801000 0x400>;
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};
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2014-12-05 15:03:23 +00:00
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2016-12-05 09:31:39 +00:00
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mioctrl@59810000 {
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compatible = "socionext,uniphier-sld8-mioctrl",
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"simple-mfd", "syscon";
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reg = <0x59810000 0x800>;
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2016-02-02 12:11:33 +00:00
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2016-12-05 09:31:39 +00:00
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mio_clk: clock {
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compatible = "socionext,uniphier-sld8-mio-clock";
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#clock-cells = <1>;
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};
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2015-06-30 09:27:00 +00:00
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2016-12-05 09:31:39 +00:00
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mio_rst: reset {
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compatible = "socionext,uniphier-sld8-mio-reset";
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#reset-cells = <1>;
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};
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};
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2015-06-30 09:27:00 +00:00
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2016-12-05 09:31:39 +00:00
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perictrl@59820000 {
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compatible = "socionext,uniphier-sld8-perictrl",
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"simple-mfd", "syscon";
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reg = <0x59820000 0x200>;
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2015-06-30 09:27:00 +00:00
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2016-12-05 09:31:39 +00:00
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peri_clk: clock {
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compatible = "socionext,uniphier-sld8-peri-clock";
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#clock-cells = <1>;
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};
|
2015-08-28 13:33:13 +00:00
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2016-12-05 09:31:39 +00:00
|
|
|
peri_rst: reset {
|
|
|
|
compatible = "socionext,uniphier-sld8-peri-reset";
|
|
|
|
#reset-cells = <1>;
|
|
|
|
};
|
|
|
|
};
|
2016-09-21 22:42:23 +00:00
|
|
|
|
2016-12-05 09:31:39 +00:00
|
|
|
sd: sdhc@5a400000 {
|
|
|
|
compatible = "socionext,uniphier-sdhc";
|
|
|
|
status = "disabled";
|
|
|
|
reg = <0x5a400000 0x200>;
|
|
|
|
interrupts = <0 76 4>;
|
|
|
|
pinctrl-names = "default", "1.8v";
|
|
|
|
pinctrl-0 = <&pinctrl_sd>;
|
|
|
|
pinctrl-1 = <&pinctrl_sd_1v8>;
|
|
|
|
clocks = <&mio_clk 0>;
|
|
|
|
reset-names = "host", "bridge";
|
|
|
|
resets = <&mio_rst 0>, <&mio_rst 3>;
|
|
|
|
bus-width = <4>;
|
|
|
|
cap-sd-highspeed;
|
|
|
|
sd-uhs-sdr12;
|
|
|
|
sd-uhs-sdr25;
|
|
|
|
sd-uhs-sdr50;
|
|
|
|
};
|
2016-09-21 22:42:23 +00:00
|
|
|
|
2016-12-05 09:31:39 +00:00
|
|
|
emmc: sdhc@5a500000 {
|
|
|
|
compatible = "socionext,uniphier-sdhc";
|
|
|
|
status = "disabled";
|
|
|
|
reg = <0x5a500000 0x200>;
|
|
|
|
interrupts = <0 78 4>;
|
|
|
|
pinctrl-names = "default", "1.8v";
|
|
|
|
pinctrl-0 = <&pinctrl_emmc>;
|
|
|
|
pinctrl-1 = <&pinctrl_emmc_1v8>;
|
|
|
|
clocks = <&mio_clk 1>;
|
|
|
|
reset-names = "host", "bridge";
|
|
|
|
resets = <&mio_rst 1>, <&mio_rst 4>;
|
|
|
|
bus-width = <8>;
|
|
|
|
non-removable;
|
|
|
|
cap-mmc-highspeed;
|
|
|
|
cap-mmc-hw-reset;
|
|
|
|
};
|
2016-02-02 12:11:36 +00:00
|
|
|
|
2016-12-05 09:31:39 +00:00
|
|
|
usb0: usb@5a800100 {
|
|
|
|
compatible = "socionext,uniphier-ehci", "generic-ehci";
|
|
|
|
status = "disabled";
|
|
|
|
reg = <0x5a800100 0x100>;
|
|
|
|
interrupts = <0 80 4>;
|
|
|
|
pinctrl-names = "default";
|
|
|
|
pinctrl-0 = <&pinctrl_usb0>;
|
|
|
|
clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
|
|
|
|
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
|
|
|
|
<&mio_rst 12>;
|
|
|
|
};
|
2016-02-02 12:11:35 +00:00
|
|
|
|
2016-12-05 09:31:39 +00:00
|
|
|
usb1: usb@5a810100 {
|
|
|
|
compatible = "socionext,uniphier-ehci", "generic-ehci";
|
|
|
|
status = "disabled";
|
|
|
|
reg = <0x5a810100 0x100>;
|
|
|
|
interrupts = <0 81 4>;
|
|
|
|
pinctrl-names = "default";
|
|
|
|
pinctrl-0 = <&pinctrl_usb1>;
|
|
|
|
clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
|
|
|
|
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
|
|
|
|
<&mio_rst 13>;
|
|
|
|
};
|
2016-02-02 12:11:34 +00:00
|
|
|
|
2016-12-05 09:31:39 +00:00
|
|
|
usb2: usb@5a820100 {
|
|
|
|
compatible = "socionext,uniphier-ehci", "generic-ehci";
|
|
|
|
status = "disabled";
|
|
|
|
reg = <0x5a820100 0x100>;
|
|
|
|
interrupts = <0 82 4>;
|
|
|
|
pinctrl-names = "default";
|
|
|
|
pinctrl-0 = <&pinctrl_usb2>;
|
|
|
|
clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
|
|
|
|
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
|
|
|
|
<&mio_rst 14>;
|
|
|
|
};
|
|
|
|
|
|
|
|
soc-glue@5f800000 {
|
|
|
|
compatible = "socionext,uniphier-sld8-soc-glue",
|
|
|
|
"simple-mfd", "syscon";
|
|
|
|
reg = <0x5f800000 0x2000>;
|
|
|
|
u-boot,dm-pre-reloc;
|
|
|
|
|
|
|
|
pinctrl: pinctrl {
|
|
|
|
compatible = "socionext,uniphier-sld8-pinctrl";
|
|
|
|
u-boot,dm-pre-reloc;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
timer@60000200 {
|
|
|
|
compatible = "arm,cortex-a9-global-timer";
|
|
|
|
reg = <0x60000200 0x20>;
|
|
|
|
interrupts = <1 11 0x104>;
|
|
|
|
clocks = <&arm_timer_clk>;
|
|
|
|
};
|
2016-09-21 22:42:23 +00:00
|
|
|
|
2016-12-05 09:31:39 +00:00
|
|
|
timer@60000600 {
|
|
|
|
compatible = "arm,cortex-a9-twd-timer";
|
|
|
|
reg = <0x60000600 0x20>;
|
|
|
|
interrupts = <1 13 0x104>;
|
|
|
|
clocks = <&arm_timer_clk>;
|
|
|
|
};
|
|
|
|
|
|
|
|
intc: interrupt-controller@60001000 {
|
|
|
|
compatible = "arm,cortex-a9-gic";
|
|
|
|
reg = <0x60001000 0x1000>,
|
|
|
|
<0x60000100 0x100>;
|
|
|
|
#interrupt-cells = <3>;
|
|
|
|
interrupt-controller;
|
|
|
|
};
|
|
|
|
|
2017-08-29 03:20:52 +00:00
|
|
|
aidet: aidet@61830000 {
|
|
|
|
compatible = "socionext,uniphier-sld8-aidet";
|
2016-12-05 09:31:39 +00:00
|
|
|
reg = <0x61830000 0x200>;
|
2017-08-29 03:20:52 +00:00
|
|
|
interrupt-controller;
|
|
|
|
#interrupt-cells = <2>;
|
2016-12-05 09:31:39 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
sysctrl@61840000 {
|
|
|
|
compatible = "socionext,uniphier-sld8-sysctrl",
|
|
|
|
"simple-mfd", "syscon";
|
|
|
|
reg = <0x61840000 0x10000>;
|
|
|
|
|
|
|
|
sys_clk: clock {
|
|
|
|
compatible = "socionext,uniphier-sld8-clock";
|
|
|
|
#clock-cells = <1>;
|
|
|
|
};
|
|
|
|
|
|
|
|
sys_rst: reset {
|
|
|
|
compatible = "socionext,uniphier-sld8-reset";
|
|
|
|
#reset-cells = <1>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
nand: nand@68000000 {
|
2017-05-15 05:23:46 +00:00
|
|
|
compatible = "socionext,uniphier-denali-nand-v5a";
|
2016-12-05 09:31:39 +00:00
|
|
|
status = "disabled";
|
|
|
|
reg-names = "nand_data", "denali_reg";
|
|
|
|
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
|
|
|
|
interrupts = <0 65 4>;
|
|
|
|
pinctrl-names = "default";
|
2017-08-29 03:20:52 +00:00
|
|
|
pinctrl-0 = <&pinctrl_nand2cs>;
|
2016-12-05 09:31:39 +00:00
|
|
|
clocks = <&sys_clk 2>;
|
|
|
|
};
|
|
|
|
};
|
2016-02-02 12:11:34 +00:00
|
|
|
};
|
2016-12-05 09:31:39 +00:00
|
|
|
|
2017-08-29 03:20:52 +00:00
|
|
|
#include "uniphier-pinctrl.dtsi"
|