2019-07-18 07:34:06 +00:00
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.. SPDX-License-Identifier: GPL-2.0+
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.. sectionauthor:: Simon Glass <sjg@chromium.org>
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Minnowboard MAX
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===============
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This uses as FSP as with Crown Bay, except it is for the Atom E3800 series.
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Download this and get the .fd file (BAYTRAIL_FSP_GOLD_003_16-SEP-2014.fd at
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the time of writing). Put it in the corresponding board directory and rename
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it to fsp.bin.
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Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same
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board directory as vga.bin.
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You still need two more binary blobs. For Minnowboard MAX, we can reuse the
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same ME firmware above, but for flash descriptor, we need get that somewhere
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else, as the one above does not seem to work, probably because it is not
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designed for the Minnowboard MAX. Now download the original firmware image
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for this board from:
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* http://firmware.intel.com/sites/default/files/2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip
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Unzip it::
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$ unzip 2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip
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Use ifdtool in the U-Boot tools directory to extract the images from that
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file, for example::
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$ ./tools/ifdtool -x MNW2MAX1.X64.0073.R02.1409160934.bin
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This will provide the descriptor file - copy this into the correct place::
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$ cp flashregion_0_flashdescriptor.bin board/intel/minnowmax/descriptor.bin
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Now you can build U-Boot and obtain u-boot.rom::
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$ make minnowmax_defconfig
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$ make all
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Checksums are as follows (but note that newer versions will invalidate this)::
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$ md5sum -b board/intel/minnowmax/*.bin
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ffda9a3b94df5b74323afb328d51e6b4 board/intel/minnowmax/descriptor.bin
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69f65b9a580246291d20d08cbef9d7c5 board/intel/minnowmax/fsp.bin
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894a97d371544ec21de9c3e8e1716c4b board/intel/minnowmax/me.bin
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a2588537da387da592a27219d56e9962 board/intel/minnowmax/vga.bin
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The ROM image is broken up into these parts:
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====== ================== ============================
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Offset Description Controlling config
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====== ================== ============================
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000000 descriptor.bin Hard-coded to 0 in ifdtool
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001000 me.bin Set by the descriptor
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500000 <spare>
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6ef000 Environment CONFIG_ENV_OFFSET
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6f0000 MRC cache CONFIG_ENABLE_MRC_CACHE
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2022-10-21 00:22:39 +00:00
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700000 u-boot-dtb.bin CONFIG_TEXT_BASE
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2019-07-18 07:34:06 +00:00
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7b0000 vga.bin CONFIG_VGA_BIOS_ADDR
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7c0000 fsp.bin CONFIG_FSP_ADDR
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7f8000 <spare> (depends on size of fsp.bin)
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7ff800 U-Boot 16-bit boot CONFIG_SYS_X86_START16
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====== ================== ============================
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Overall ROM image size is controlled by CONFIG_ROM_SIZE.
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Note that the debug version of the FSP is bigger in size. If this version
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is used, CONFIG_FSP_ADDR needs to be configured to 0xfffb0000 instead of
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the default value 0xfffc0000.
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