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u-boot/drivers/pinctrl/nxp/Kconfig

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pinctrl: imx: Introduce pinctrl driver for i.MX6 Introduce pinctrl for i.MX6 1. pinctrl-imx.c is for common usage. It's used by i.MX6/7. 2. Add PINCTRL_IMX PINCTRL_IMX6 Kconfig entry. 3. To the pinctrl_ops implementation, only set_state is implemented. To i.MX6/7, the pinctrl dts entry is as following: &iomuxc { pinctrl-names = "default"; pinctrl_csi1: csi1grp { fsl,pins = < MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 >; }; [.....] }; there is no property named function or groups. So pinctrl_generic_set_state can not be used here. 5. This driver is a simple implementation for i.mx iomux controller, only parse the fsl,pins property and write value to registers. 6. With DEBUG enabled, we can see log when "i2c bus 0": " set_state_simple op missing imx_pinctrl_set_state: i2c1grp mux_reg 0x14c, conf_reg 0x3bc, input_reg 0x5d8, mux_mode 0x0, input_val 0x1, config_val 0x4000007f write mux: offset 0x14c val 0x10 select_input: offset 0x5d8 val 0x1 write config: offset 0x3bc val 0x7f mux_reg 0x148, conf_reg 0x3b8, input_reg 0x5d4, mux_mode 0x0, input_val 0x1, config_val 0x4000007f write mux: offset 0x148 val 0x10 select_input: offset 0x5d4 val 0x1 write config: offset 0x3b8 val 0x7f " this means imx6 pinctrl driver works as expected. Signed-off-by: Peng Fan <van.freenix@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-03 02:06:07 +00:00
config PINCTRL_IMX
bool
pinctrl: Add pinctrl driver for i.MX8 Add pinctrl driver for i.MX8. The pads configuration is controlled by SCU, so need to ask SCU to configure pads through scfw API. Add pinctrl-scu to invoke sc_pad_set to configure pads. Add a new flag IMX8_USE_SCU to differentiate i.MX8 from other platforms which could directly configure pads from Acore side. Add CONFIG_PINCTRL_IMX8 as the built gate. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
2018-10-18 12:28:28 +00:00
config PINCTRL_IMX_SCU
bool
arm: imx: add i.MX53 Beckhoff CX9020 Embedded PC Add CX9020 board based on mx53loco. Add simplified imx53 base device tree from kernel v4.8-rc8, to reuse serial_mxc with DTE and prepare for device tree migration of other functions and imx53 devices. The CX9020 differs from i.MX53 Quick Start Board by: - use uart2 instead of uart1 - DVI-D connector instead of VGA - no audio - CCAT FPGA connected to emi - enable rtc Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
2016-11-04 10:57:02 +00:00
config PINCTRL_IMX5
bool "IMX5 pinctrl driver"
depends on ARCH_MX5 && PINCTRL_FULL
select DEVRES
select PINCTRL_IMX
help
Say Y here to enable the imx5 pinctrl driver
This provides a simple pinctrl driver for i.MX 53SoC familiy,
i.MX53. This feature depends on device tree
configuration. This driver is different from the linux one,
this is a simple implementation, only parses the 'fsl,pins'
property and configure related registers.
pinctrl: imx: Introduce pinctrl driver for i.MX6 Introduce pinctrl for i.MX6 1. pinctrl-imx.c is for common usage. It's used by i.MX6/7. 2. Add PINCTRL_IMX PINCTRL_IMX6 Kconfig entry. 3. To the pinctrl_ops implementation, only set_state is implemented. To i.MX6/7, the pinctrl dts entry is as following: &iomuxc { pinctrl-names = "default"; pinctrl_csi1: csi1grp { fsl,pins = < MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 >; }; [.....] }; there is no property named function or groups. So pinctrl_generic_set_state can not be used here. 5. This driver is a simple implementation for i.mx iomux controller, only parse the fsl,pins property and write value to registers. 6. With DEBUG enabled, we can see log when "i2c bus 0": " set_state_simple op missing imx_pinctrl_set_state: i2c1grp mux_reg 0x14c, conf_reg 0x3bc, input_reg 0x5d8, mux_mode 0x0, input_val 0x1, config_val 0x4000007f write mux: offset 0x14c val 0x10 select_input: offset 0x5d8 val 0x1 write config: offset 0x3bc val 0x7f mux_reg 0x148, conf_reg 0x3b8, input_reg 0x5d4, mux_mode 0x0, input_val 0x1, config_val 0x4000007f write mux: offset 0x148 val 0x10 select_input: offset 0x5d4 val 0x1 write config: offset 0x3b8 val 0x7f " this means imx6 pinctrl driver works as expected. Signed-off-by: Peng Fan <van.freenix@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-03 02:06:07 +00:00
config PINCTRL_IMX6
bool "IMX6 pinctrl driver"
depends on ARCH_MX6 && PINCTRL_FULL
select DEVRES
select PINCTRL_IMX
help
Say Y here to enable the imx6 pinctrl driver
This provides a simple pinctrl driver for i.MX6 SoC familiy,
i.MX6DQ/SL/SX/UL/DQP. This feature depends on device tree
configuration. This driver is different from the linux one,
this is a simple implementation, only parses the 'fsl,pins'
property and configure related registers.
pinctrl: imx: Support i.MX7D Introudce i.MX7 pinctrl driver support. For now only i.MX7D supported. There are two iomux controllers in i.MX7D, iomuxc and iomuxc_lpsr. To iomuxc_lpsr, ZERO_OFFSET_VALID is set, means offset of mux_reg and conf_reg can begin at 0. Signed-off-by: Peng Fan <van.freenix@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-03 02:06:08 +00:00
config PINCTRL_IMX7
bool "IMX7 pinctrl driver"
depends on ARCH_MX7 && PINCTRL_FULL
select DEVRES
select PINCTRL_IMX
help
Say Y here to enable the imx7 pinctrl driver
This provides a simple pinctrl driver for i.MX7 SoC familiy,
i.MX7D. This feature depends on device tree
configuration. This driver is different from the linux one,
this is a simple implementation, only parses the 'fsl,pins'
property and configure related registers.
pinctrl: Add i.MX7ULP pinctrl driver Add i.MX7ULP pinctrl driver. Select CONFIG_PINCTRL_IMX7ULP to use this driver. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by : Stefano Babic <sbabic@denx.de>
2017-02-22 08:21:49 +00:00
config PINCTRL_IMX7ULP
bool "IMX7ULP pinctrl driver"
depends on ARCH_MX7ULP && PINCTRL_FULL
select DEVRES
select PINCTRL_IMX
help
Say Y here to enable the imx7ulp pinctrl driver
This provides a simple pinctrl driver for i.MX7ULP SoC familiy.
This feature depends on device tree configuration. This driver
is different from the linux one, this is a simple implementation,
only parses the 'fsl,pins' property and configure related
registers.
pinctrl: Add pinctrl driver for i.MX8 Add pinctrl driver for i.MX8. The pads configuration is controlled by SCU, so need to ask SCU to configure pads through scfw API. Add pinctrl-scu to invoke sc_pad_set to configure pads. Add a new flag IMX8_USE_SCU to differentiate i.MX8 from other platforms which could directly configure pads from Acore side. Add CONFIG_PINCTRL_IMX8 as the built gate. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
2018-10-18 12:28:28 +00:00
config PINCTRL_IMX8
bool "IMX8 pinctrl driver"
depends on ARCH_IMX8 && PINCTRL_FULL
select DEVRES
select PINCTRL_IMX
select PINCTRL_IMX_SCU
help
Say Y here to enable the imx8 pinctrl driver
This provides a simple pinctrl driver for i.MX8 SoC familiy.
This feature depends on device tree configuration. This driver
is different from the linux one, this is a simple implementation,
only parses the 'fsl,pins' property and configures related
registers.
ARM: vybrid: Provide pinctrl driver for Vybrid (vf610) This implementation comply with other iMX devices pinctrl drivers already available in U-boot. Signed-off-by: Lukasz Majewski <lukma@denx.de>
2018-11-19 23:38:06 +00:00
pinctrl: add imx8m driver Add i.mx8m pinctrl driver. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-28 09:43:42 +00:00
config PINCTRL_IMX8M
bool "IMX8M pinctrl driver"
depends on ARCH_IMX8M && PINCTRL_FULL
select DEVRES
select PINCTRL_IMX
help
Say Y here to enable the imx8m pinctrl driver
This provides a simple pinctrl driver for i.MX8M SoC familiy.
This feature depends on device tree configuration. This driver
is different from the linux one, this is a simple implementation,
only parses the 'fsl,pins' property and configure related
registers.
pinctrl: mxs: Add support for i.MX2[38] mxs pinctrl driver The code responsible for setting proper values in the MUX registers (in the mxs_pinctrl_set_state()) has been ported from Linux kernel - SHA1: 17bb763e7eaf tag v5.1.11 from linux-stable. As the pinctrl node in the imx28.dtsi file has gpio pins nodes as subnodes, it was necessary to use 'dm_scan_fdt_dev()' (as a .bind method) to also make them 'visible' by the DM's "gpio_mxs" driver. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Marek Vasut <marex@denx.de>
2019-06-19 15:31:06 +00:00
config PINCTRL_MXS
bool "NXP MXS pinctrl driver"
depends on ARCH_MX28 && PINCTRL_FULL
help
Say Y here to enable the i.MX mxs pinctrl driver
This option provides a simple pinctrl driver for i.MX mxs SoC
familiy, e.g. i.MX28. This feature depends on device tree
configuration.
pinctrl: add i.MXRT driver Add i.MXRT pinctrl driver. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-10 14:47:02 +00:00
config PINCTRL_IMXRT
bool "IMXRT pinctrl driver"
depends on ARCH_IMXRT && PINCTRL_FULL
select DEVRES
select PINCTRL_IMX
help
Say Y here to enable the imxrt pinctrl driver
This provides a simple pinctrl driver for i.MXRT SoC familiy.
This feature depends on device tree configuration. This driver
is different from the linux one, this is a simple implementation,
only parses the 'fsl,pins' property and configure related
registers.
ARM: vybrid: Provide pinctrl driver for Vybrid (vf610) This implementation comply with other iMX devices pinctrl drivers already available in U-boot. Signed-off-by: Lukasz Majewski <lukma@denx.de>
2018-11-19 23:38:06 +00:00
config PINCTRL_VYBRID
bool "Vybrid (vf610) pinctrl driver"
depends on ARCH_VF610 && PINCTRL_FULL
select DEVRES
select PINCTRL_IMX
help
Say Y here to enable the Vybrid (vf610) pinctrl driver
This provides a simple pinctrl driver for Vybrid SoC familiy,
vf610. This feature depends on device tree
configuration. This driver is different from the linux one,
this is a simple implementation, only parses the 'fsl,pins'
property and configure related registers.
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