2015-04-15 03:03:42 +00:00
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/*
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* Copyright 2014 Google Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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*/
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#include <common.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <lcd.h>
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#include <asm/gpio.h>
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#include <asm/arch-tegra/clk_rst.h>
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#include <asm/arch/clock.h>
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#include <asm/arch-tegra/dc.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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enum {
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/* Maximum LCD size we support */
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LCD_MAX_WIDTH = 1920,
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LCD_MAX_HEIGHT = 1200,
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LCD_MAX_LOG2_BPP = 4, /* 2^4 = 16 bpp */
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};
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vidinfo_t panel_info = {
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/* Insert a value here so that we don't end up in the BSS */
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.vl_col = -1,
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};
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int tegra_lcd_check_next_stage(const void *blob, int wait)
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{
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return 0;
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}
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void tegra_lcd_early_init(const void *blob)
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{
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/*
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* Go with the maximum size for now. We will fix this up after
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* relocation. These values are only used for memory alocation.
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*/
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panel_info.vl_col = LCD_MAX_WIDTH;
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panel_info.vl_row = LCD_MAX_HEIGHT;
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panel_info.vl_bpix = LCD_MAX_LOG2_BPP;
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}
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static int tegra124_lcd_init(void *lcdbase)
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{
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struct display_timing timing;
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int ret;
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clock_set_up_plldp();
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2015-06-05 20:39:41 +00:00
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clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH, 408000000);
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2015-04-15 03:03:42 +00:00
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clock_enable(PERIPH_ID_HOST1X);
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clock_enable(PERIPH_ID_DISP1);
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clock_enable(PERIPH_ID_PWM);
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clock_enable(PERIPH_ID_DPAUX);
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clock_enable(PERIPH_ID_SOR0);
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udelay(2);
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reset_set_enable(PERIPH_ID_HOST1X, 0);
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reset_set_enable(PERIPH_ID_DISP1, 0);
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reset_set_enable(PERIPH_ID_PWM, 0);
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reset_set_enable(PERIPH_ID_DPAUX, 0);
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reset_set_enable(PERIPH_ID_SOR0, 0);
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ret = display_init(lcdbase, 1 << LCD_BPP, &timing);
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if (ret)
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return ret;
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panel_info.vl_col = roundup(timing.hactive.typ, 16);
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panel_info.vl_row = timing.vactive.typ;
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lcd_set_flush_dcache(1);
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return 0;
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}
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void lcd_ctrl_init(void *lcdbase)
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{
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ulong start;
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int ret;
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start = get_timer(0);
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ret = tegra124_lcd_init(lcdbase);
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debug("LCD init took %lu ms\n", get_timer(start));
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if (ret)
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printf("%s: Error %d\n", __func__, ret);
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}
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void lcd_enable(void)
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{
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}
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