u-boot/drivers/cache/Kconfig

#
# Cache controllers
#

menu "Cache Controller drivers"

config CACHE
	bool "Enable Driver Model for Cache controllers"
	depends on DM
	help
	  Enable driver model for cache controllers that are found on
	  most CPU's. Cache is memory that the CPU can access directly and
	  is usually located on the same chip. This uclass can be used for
	  configuring settings that be found from a device tree file.

config L2X0_CACHE
	tristate "PL310 cache driver"
	select CACHE
	depends on ARM
	help
	  This driver is for the PL310 cache controller commonly found on
	  ARMv7(32-bit) devices. The driver configures the cache settings
	  found in the device tree.

config V5L2_CACHE
	bool "Andes V5L2 cache driver"
	select CACHE
	depends on RISCV_NDS_CACHE
	help
	  Support Andes V5L2 cache controller in AE350 platform.
	  It will configure tag and data ram timing control from the
	  device tree and enable L2 cache.

endmenu
dm: cache: Create a uclass for cache The cache UCLASS will be used for configure settings that can be found in a CPU's L2 cache controller. Add a uclass and a test for cache. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> 2019-04-23 21:55:03 +00:00			`#`
			`# Cache controllers`
			`#`

			`menu "Cache Controller drivers"`

			`config CACHE`
			`bool "Enable Driver Model for Cache controllers"`
			`depends on DM`
			`help`
			`Enable driver model for cache controllers that are found on`
			`most CPU's. Cache is memory that the CPU can access directly and`
			`is usually located on the same chip. This uclass can be used for`
			`configuring settings that be found from a device tree file.`

dm: cache: add the pl310 cache controller driver Add a PL310 cache controller driver that is usually found on ARMv7(32-bit) devices. The driver configures the cache settings that can be found in the device tree files. This initial revision only configures basic settings(data & instruction prefetch, shared-override, data & tag latency). I believe these are the settings that affect performance the most. Comprehensive settings can be done by the OS. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> 2019-04-23 21:55:04 +00:00			`config L2X0_CACHE`
			`tristate "PL310 cache driver"`
			`select CACHE`
			`depends on ARM`
			`help`
			`This driver is for the PL310 cache controller commonly found on`
			`ARMv7(32-bit) devices. The driver configures the cache settings`
			`found in the device tree.`

dm: cache: add v5l2 cache controller driver Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse the cache settings from the dtb. In this version tag and data ram control timing can be adjusted by the requirement from the dtb. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 2019-08-28 10:46:06 +00:00			`config V5L2_CACHE`
			`bool "Andes V5L2 cache driver"`
			`select CACHE`
			`depends on RISCV_NDS_CACHE`
			`help`
			`Support Andes V5L2 cache controller in AE350 platform.`
			`It will configure tag and data ram timing control from the`
			`device tree and enable L2 cache.`

dm: cache: Create a uclass for cache The cache UCLASS will be used for configure settings that can be found in a CPU's L2 cache controller. Add a uclass and a test for cache. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> 2019-04-23 21:55:03 +00:00			`endmenu`