2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2008-05-08 16:52:25 +00:00
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/*
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* (C) Copyright 2007-2008
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2011-10-31 23:00:39 +00:00
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* Stelian Pop <stelian@popies.net>
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2008-05-08 16:52:25 +00:00
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* Configuation settings for the AT91SAM9RLEK board.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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2011-08-01 03:56:53 +00:00
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#include <asm/hardware.h>
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2008-05-08 16:52:25 +00:00
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/* ARM asynchronous clock */
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2011-08-01 03:56:53 +00:00
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#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
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#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */
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2008-05-08 16:52:25 +00:00
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/*
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* Hardware drivers
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*/
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2011-08-01 03:56:53 +00:00
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2008-05-08 12:52:32 +00:00
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/* LCD */
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#define LCD_BPP LCD_COLOR8
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2011-08-01 03:56:53 +00:00
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2008-05-08 16:52:25 +00:00
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/* SDRAM */
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2011-08-01 03:56:53 +00:00
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#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
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#define CONFIG_SYS_SDRAM_SIZE 0x04000000
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2022-05-25 16:16:03 +00:00
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#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024)
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#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM
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2008-05-08 16:52:25 +00:00
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/* NAND flash */
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2009-03-22 09:22:34 +00:00
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#ifdef CONFIG_CMD_NAND
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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2011-08-01 03:56:53 +00:00
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#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_NAND_DBW_8 1
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2009-03-22 09:22:34 +00:00
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/* our ALE is AD21 */
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#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
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/* our CLE is AD22 */
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#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
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#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PB6
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#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD17
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2009-07-18 19:52:24 +00:00
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2009-03-22 09:22:34 +00:00
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#endif
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2008-05-08 16:52:25 +00:00
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#endif
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