u-boot/arch/arm/mach-rmobile/Kconfig.rza1

if RZA1

# required by the Ethernet driver
config R7S72100
	bool
	default y

# required by serial and usb driver
config CPU_RZA1
	bool
	default y

choice
	prompt "Renesas RZ/A1 board select"

# Renesas Supported Boards
config TARGET_GRPEACH
	bool "GR-PEACH board"

endchoice

# Renesas Supported Boards
source "board/renesas/grpeach/Kconfig"

endif
ARM: dts: renesas: Add RZ/A1 platform code Add platform code and DTs for Renesas RZ/A1 R7S72100 SoC. Distinguishing feature of this SoC is that it has up to 10 MiB of on-SoC static RAM (SRAM). The DTs are imported from Linux 5.0.11, commit d5a2675b207d . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 2017-08-23 14:53:59 -05:00			`if RZA1`

			`# required by the Ethernet driver`
			`config R7S72100`
			`bool`
			`default y`

			`# required by serial and usb driver`
			`config CPU_RZA1`
			`bool`
			`default y`

			`choice`
			`prompt "Renesas RZ/A1 board select"`

ARM: dts: renesas: Add RZ/A1 GR-Peach board Add board code and DTs for Renesas RZ/A1 SoC-based GR-Peach, which is a cheap development platform with RZ/A1H SoC. The DTs are imported from Linux 5.0.11, commit d5a2675b207d . Currently supported are UART, ethernet and RPC SPI. The board can be booted from RPC SPI by writing the u-boot.bin binary to the beginning of the SPI NOR, e.g. using the "sf" command. The board can also be booted via JTAG by setting text base to 0x20020000, loading u-boot.bin there via JTAG and executing it from that address. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 2017-08-23 14:53:59 -05:00			`# Renesas Supported Boards`
			`config TARGET_GRPEACH`
			`bool "GR-PEACH board"`

ARM: dts: renesas: Add RZ/A1 platform code Add platform code and DTs for Renesas RZ/A1 R7S72100 SoC. Distinguishing feature of this SoC is that it has up to 10 MiB of on-SoC static RAM (SRAM). The DTs are imported from Linux 5.0.11, commit d5a2675b207d . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 2017-08-23 14:53:59 -05:00			`endchoice`

ARM: dts: renesas: Add RZ/A1 GR-Peach board Add board code and DTs for Renesas RZ/A1 SoC-based GR-Peach, which is a cheap development platform with RZ/A1H SoC. The DTs are imported from Linux 5.0.11, commit d5a2675b207d . Currently supported are UART, ethernet and RPC SPI. The board can be booted from RPC SPI by writing the u-boot.bin binary to the beginning of the SPI NOR, e.g. using the "sf" command. The board can also be booted via JTAG by setting text base to 0x20020000, loading u-boot.bin there via JTAG and executing it from that address. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 2017-08-23 14:53:59 -05:00			`# Renesas Supported Boards`
			`source "board/renesas/grpeach/Kconfig"`

ARM: dts: renesas: Add RZ/A1 platform code Add platform code and DTs for Renesas RZ/A1 R7S72100 SoC. Distinguishing feature of this SoC is that it has up to 10 MiB of on-SoC static RAM (SRAM). The DTs are imported from Linux 5.0.11, commit d5a2675b207d . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 2017-08-23 14:53:59 -05:00			`endif`