mirror of
https://github.com/AsahiLinux/u-boot
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122 lines
3.1 KiB
Text
122 lines
3.1 KiB
Text
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) Siemens AG, 2018-2023
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*
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* Authors:
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* Chao Zeng <chao.zeng@siemens.com>
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* Jan Kiszka <jan.kiszka@siemens.com>
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*
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* AM6548-based (quad-core) IOT2050 M.2 variant (based on Advanced Product
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* Generation 2), 2 GB RAM, 16 GB eMMC, USB-serial converter on connector X30
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*
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* Product homepage:
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* https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html
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*/
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#include "k3-am6548-iot2050-advanced-common.dtsi"
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#include "k3-am65-iot2050-common-pg2.dtsi"
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/ {
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compatible = "siemens,iot2050-advanced-m2", "ti,am654";
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model = "SIMATIC IOT2050 Advanced M2";
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};
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&mcu_r5fss0 {
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/* lock-step mode not supported on this board */
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ti,cluster-mode = <0>;
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};
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&main_pmx0 {
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main_m2_enable_pins_default: main-m2-enable-pins-default {
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pinctrl-single,pins = <
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AM65X_IOPAD(0x01c4, PIN_INPUT_PULLUP, 7) /* (AH13) GPIO1_17 */
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>;
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};
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main_bkey_pcie_reset: main-bkey-pcie-reset {
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pinctrl-single,pins = <
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AM65X_IOPAD(0x01bc, PIN_OUTPUT_PULLUP, 7) /* (AG13) GPIO1_15 */
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>;
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};
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main_pmx0_m2_config_pins_default: main-pmx0-m2-config-pins-default {
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pinctrl-single,pins = <
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AM65X_IOPAD(0x01c8, PIN_INPUT_PULLUP, 7) /* (AE13) GPIO1_18 */
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AM65X_IOPAD(0x01cc, PIN_INPUT_PULLUP, 7) /* (AD13) GPIO1_19 */
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>;
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};
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main_m2_pcie_mux_control: main-m2-pcie-mux-control {
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pinctrl-single,pins = <
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AM65X_IOPAD(0x0148, PIN_INPUT_PULLUP, 7) /* (AG22) GPIO0_82 */
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AM65X_IOPAD(0x0160, PIN_INPUT_PULLUP, 7) /* (AE20) GPIO0_88 */
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AM65X_IOPAD(0x0164, PIN_INPUT_PULLUP, 7) /* (AF19) GPIO0_89 */
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>;
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};
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};
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&main_pmx1 {
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main_pmx1_m2_config_pins_default: main-pmx1-m2-config-pins-default {
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pinctrl-single,pins = <
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AM65X_IOPAD(0x0018, PIN_INPUT_PULLUP, 7) /* (B22) GPIO1_88 */
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AM65X_IOPAD(0x001c, PIN_INPUT_PULLUP, 7) /* (C23) GPIO1_89 */
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>;
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};
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};
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&main_gpio0 {
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pinctrl-names = "default";
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pinctrl-0 = <
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&main_m2_pcie_mux_control
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&arduino_io_d4_to_d9_pins_default
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>;
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};
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&main_gpio1 {
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pinctrl-names = "default";
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pinctrl-0 = <
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&main_m2_enable_pins_default
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&main_pmx0_m2_config_pins_default
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&main_pmx1_m2_config_pins_default
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&cp2102n_reset_pin_default
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>;
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};
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/*
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* Base configuration for B-key slot with PCIe x2, E-key with USB 2.0 only.
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* Firmware switches to other modes via device tree overlays.
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*/
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&serdes0 {
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assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
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assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
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};
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&pcie0_rc {
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pinctrl-names = "default";
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pinctrl-0 = <&main_bkey_pcie_reset>;
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num-lanes = <2>;
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phys = <&serdes0 PHY_TYPE_PCIE 1>, <&serdes1 PHY_TYPE_PCIE 1>;
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phy-names = "pcie-phy0","pcie-phy1";
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reset-gpios = <&main_gpio1 15 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&pcie1_rc {
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status = "disabled";
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};
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&dwc3_0 {
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assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
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<&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
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/delete-property/ phys;
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/delete-property/ phy-names;
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};
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&usb0 {
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maximum-speed = "high-speed";
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/delete-property/ snps,dis-u1-entry-quirk;
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/delete-property/ snps,dis-u2-entry-quirk;
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};
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