2002-11-03 00:24:07 +00:00
|
|
|
/*
|
|
|
|
* (C) Copyright 2002
|
|
|
|
* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
|
|
|
|
* Keith Outwater, keith_outwater@mvis.com.
|
|
|
|
*
|
|
|
|
* See file CREDITS for list of people who contributed to this
|
|
|
|
* project.
|
|
|
|
*
|
|
|
|
* This program is free software; you can redistribute it and/or
|
|
|
|
* modify it under the terms of the GNU General Public License as
|
|
|
|
* published by the Free Software Foundation; either version 2 of
|
|
|
|
* the License, or (at your option) any later version.
|
|
|
|
*
|
|
|
|
* This program is distributed in the hope that it will be useful,
|
|
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
|
|
* GNU General Public License for more details.
|
|
|
|
*
|
|
|
|
* You should have received a copy of the GNU General Public License
|
|
|
|
* along with this program; if not, write to the Free Software
|
|
|
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
|
|
* MA 02111-1307 USA
|
|
|
|
*
|
|
|
|
*/
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Virtex2 FPGA configuration support for the GEN860T computer
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include <common.h>
|
|
|
|
#include <virtex2.h>
|
|
|
|
#include <command.h>
|
|
|
|
#include "fpga.h"
|
|
|
|
|
2006-03-31 16:32:53 +00:00
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
|
2007-12-27 16:12:34 +00:00
|
|
|
#if defined(CONFIG_FPGA)
|
2002-11-03 00:24:07 +00:00
|
|
|
|
|
|
|
#if 0
|
|
|
|
#define GEN860T_FPGA_DEBUG
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef GEN860T_FPGA_DEBUG
|
|
|
|
#define PRINTF(fmt,args...) printf (fmt ,##args)
|
|
|
|
#else
|
|
|
|
#define PRINTF(fmt,args...)
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Port bit numbers for the Selectmap controls
|
|
|
|
*/
|
|
|
|
#define FPGA_INIT_BIT_NUM 22 /* PB22 */
|
|
|
|
#define FPGA_RESET_BIT_NUM 11 /* PC11 */
|
|
|
|
#define FPGA_DONE_BIT_NUM 16 /* PB16 */
|
|
|
|
#define FPGA_PROGRAM_BIT_NUM 7 /* PA7 */
|
|
|
|
|
|
|
|
/* Note that these are pointers to code that is in Flash. They will be
|
|
|
|
* relocated at runtime.
|
|
|
|
*/
|
|
|
|
Xilinx_Virtex2_Slave_SelectMap_fns fpga_fns = {
|
|
|
|
fpga_pre_config_fn,
|
|
|
|
fpga_pgm_fn,
|
|
|
|
fpga_init_fn,
|
|
|
|
fpga_err_fn,
|
|
|
|
fpga_done_fn,
|
|
|
|
fpga_clk_fn,
|
|
|
|
fpga_cs_fn,
|
|
|
|
fpga_wr_fn,
|
|
|
|
fpga_read_data_fn,
|
|
|
|
fpga_write_data_fn,
|
|
|
|
fpga_busy_fn,
|
|
|
|
fpga_abort_fn,
|
|
|
|
fpga_post_config_fn
|
|
|
|
};
|
|
|
|
|
|
|
|
Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
|
2004-02-12 00:47:09 +00:00
|
|
|
{Xilinx_Virtex2,
|
|
|
|
slave_selectmap,
|
|
|
|
XILINX_XC2V3000_SIZE,
|
|
|
|
(void *) &fpga_fns,
|
|
|
|
0}
|
2002-11-03 00:24:07 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Display FPGA revision information
|
|
|
|
*/
|
2004-02-12 00:47:09 +00:00
|
|
|
void print_fpga_revision (void)
|
2002-11-03 00:24:07 +00:00
|
|
|
{
|
2004-02-12 00:47:09 +00:00
|
|
|
vu_long *rev_p = (vu_long *) 0x60000008;
|
|
|
|
|
|
|
|
printf ("FPGA Revision 0x%.8lx"
|
|
|
|
" (Date %.2lx/%.2lx/%.2lx, Status \"%.1lx\", Version %.3lu)\n",
|
|
|
|
*rev_p,
|
|
|
|
((*rev_p >> 28) & 0xf),
|
|
|
|
((*rev_p >> 20) & 0xff),
|
|
|
|
((*rev_p >> 12) & 0xff),
|
|
|
|
((*rev_p >> 8) & 0xf), (*rev_p & 0xff));
|
2002-11-03 00:24:07 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Perform a simple test of the FPGA to processor interface using the FPGA's
|
|
|
|
* inverting bus test register. The great thing about doing a read/write
|
|
|
|
* test on a register that inverts it's contents is that you avoid any
|
|
|
|
* problems with bus charging.
|
|
|
|
* Return 0 on failure, 1 on success.
|
|
|
|
*/
|
2004-02-12 00:47:09 +00:00
|
|
|
int test_fpga_ibtr (void)
|
2002-11-03 00:24:07 +00:00
|
|
|
{
|
2004-02-12 00:47:09 +00:00
|
|
|
vu_long *ibtr_p = (vu_long *) 0x60000010;
|
2002-11-03 00:24:07 +00:00
|
|
|
vu_long readback;
|
|
|
|
vu_long compare;
|
|
|
|
int i;
|
|
|
|
int j;
|
|
|
|
int k;
|
|
|
|
int pass = 1;
|
|
|
|
|
|
|
|
static const ulong bitpattern[] = {
|
2004-02-12 00:47:09 +00:00
|
|
|
0xdeadbeef, /* magic ID pattern for debug */
|
|
|
|
0x00000001, /* single bit */
|
|
|
|
0x00000003, /* two adjacent bits */
|
|
|
|
0x00000007, /* three adjacent bits */
|
|
|
|
0x0000000F, /* four adjacent bits */
|
|
|
|
0x00000005, /* two non-adjacent bits */
|
|
|
|
0x00000015, /* three non-adjacent bits */
|
|
|
|
0x00000055, /* four non-adjacent bits */
|
|
|
|
0xaaaaaaaa, /* alternating 1/0 */
|
2002-11-03 00:24:07 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
for (i = 0; i < 1024; i++) {
|
|
|
|
for (j = 0; j < 31; j++) {
|
2004-02-12 00:47:09 +00:00
|
|
|
for (k = 0;
|
|
|
|
k < sizeof (bitpattern) / sizeof (bitpattern[0]);
|
|
|
|
k++) {
|
2002-11-03 00:24:07 +00:00
|
|
|
*ibtr_p = compare = (bitpattern[k] << j);
|
|
|
|
readback = *ibtr_p;
|
|
|
|
if (readback != ~compare) {
|
2004-02-12 00:47:09 +00:00
|
|
|
printf ("%s:%d: FPGA test fail: expected 0x%.8lx" " actual 0x%.8lx\n", __FUNCTION__, __LINE__, ~compare, readback);
|
2002-11-03 00:24:07 +00:00
|
|
|
pass = 0;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2004-02-12 00:47:09 +00:00
|
|
|
if (!pass)
|
|
|
|
break;
|
2002-11-03 00:24:07 +00:00
|
|
|
}
|
2004-02-12 00:47:09 +00:00
|
|
|
if (!pass)
|
|
|
|
break;
|
2002-11-03 00:24:07 +00:00
|
|
|
}
|
|
|
|
if (pass) {
|
2004-02-12 00:47:09 +00:00
|
|
|
printf ("FPGA inverting bus test passed\n");
|
|
|
|
print_fpga_revision ();
|
|
|
|
} else {
|
|
|
|
printf ("** FPGA inverting bus test failed\n");
|
2002-11-03 00:24:07 +00:00
|
|
|
}
|
|
|
|
return pass;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Set the active-low FPGA reset signal.
|
|
|
|
*/
|
2004-02-12 00:47:09 +00:00
|
|
|
void fpga_reset (int assert)
|
2002-11-03 00:24:07 +00:00
|
|
|
{
|
2008-10-16 13:01:15 +00:00
|
|
|
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
|
2002-11-03 00:24:07 +00:00
|
|
|
|
2004-02-12 00:47:09 +00:00
|
|
|
PRINTF ("%s:%d: RESET ", __FUNCTION__, __LINE__);
|
2002-11-03 00:24:07 +00:00
|
|
|
if (assert) {
|
|
|
|
immap->im_ioport.iop_pcdat &= ~(0x8000 >> FPGA_RESET_BIT_NUM);
|
2004-02-12 00:47:09 +00:00
|
|
|
PRINTF ("asserted\n");
|
|
|
|
} else {
|
2002-11-03 00:24:07 +00:00
|
|
|
immap->im_ioport.iop_pcdat |= (0x8000 >> FPGA_RESET_BIT_NUM);
|
2004-02-12 00:47:09 +00:00
|
|
|
PRINTF ("deasserted\n");
|
2002-11-03 00:24:07 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialize the SelectMap interface. We assume that the mode and the
|
|
|
|
* initial state of all of the port pins have already been set!
|
|
|
|
*/
|
2004-02-12 00:47:09 +00:00
|
|
|
void fpga_selectmap_init (void)
|
2002-11-03 00:24:07 +00:00
|
|
|
{
|
2004-02-12 00:47:09 +00:00
|
|
|
PRINTF ("%s:%d: Initialize SelectMap interface\n", __FUNCTION__,
|
|
|
|
__LINE__);
|
2013-04-01 18:29:11 +00:00
|
|
|
fpga_pgm_fn(false, false, 0); /* make sure program pin is inactive */
|
2002-11-03 00:24:07 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialize the fpga. Return 1 on success, 0 on failure.
|
|
|
|
*/
|
2004-02-12 00:47:09 +00:00
|
|
|
int gen860t_init_fpga (void)
|
2002-11-03 00:24:07 +00:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
2009-09-21 16:20:32 +00:00
|
|
|
PRINTF ("%s:%d: Initialize FPGA interface\n",
|
|
|
|
__FUNCTION__, __LINE__);
|
|
|
|
fpga_init ();
|
2004-02-12 00:47:09 +00:00
|
|
|
fpga_selectmap_init ();
|
2002-11-03 00:24:07 +00:00
|
|
|
|
2004-02-12 00:47:09 +00:00
|
|
|
for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
|
|
|
|
PRINTF ("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i);
|
|
|
|
fpga_add (fpga_xilinx, &fpga[i]);
|
2002-11-03 00:24:07 +00:00
|
|
|
}
|
2004-02-12 00:47:09 +00:00
|
|
|
return 1;
|
2002-11-03 00:24:07 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Set the FPGA's active-low SelectMap program line to the specified level
|
|
|
|
*/
|
2004-02-12 00:47:09 +00:00
|
|
|
int fpga_pgm_fn (int assert, int flush, int cookie)
|
2002-11-03 00:24:07 +00:00
|
|
|
{
|
2008-10-16 13:01:15 +00:00
|
|
|
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
|
2002-11-03 00:24:07 +00:00
|
|
|
|
2004-02-12 00:47:09 +00:00
|
|
|
PRINTF ("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__);
|
2002-11-03 00:24:07 +00:00
|
|
|
|
|
|
|
if (assert) {
|
2004-02-12 00:47:09 +00:00
|
|
|
immap->im_ioport.iop_padat &=
|
|
|
|
~(0x8000 >> FPGA_PROGRAM_BIT_NUM);
|
|
|
|
PRINTF ("asserted\n");
|
|
|
|
} else {
|
|
|
|
immap->im_ioport.iop_padat |=
|
|
|
|
(0x8000 >> FPGA_PROGRAM_BIT_NUM);
|
|
|
|
PRINTF ("deasserted\n");
|
2002-11-03 00:24:07 +00:00
|
|
|
}
|
|
|
|
return assert;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Test the state of the active-low FPGA INIT line. Return 1 on INIT
|
|
|
|
* asserted (low).
|
|
|
|
*/
|
2004-02-12 00:47:09 +00:00
|
|
|
int fpga_init_fn (int cookie)
|
2002-11-03 00:24:07 +00:00
|
|
|
{
|
2008-10-16 13:01:15 +00:00
|
|
|
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
|
2002-11-03 00:24:07 +00:00
|
|
|
|
2004-02-12 00:47:09 +00:00
|
|
|
PRINTF ("%s:%d: INIT check... ", __FUNCTION__, __LINE__);
|
|
|
|
if (immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_INIT_BIT_NUM)) {
|
|
|
|
PRINTF ("high\n");
|
2002-11-03 00:24:07 +00:00
|
|
|
return 0;
|
2004-02-12 00:47:09 +00:00
|
|
|
} else {
|
|
|
|
PRINTF ("low\n");
|
2002-11-03 00:24:07 +00:00
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Test the state of the active-high FPGA DONE pin
|
|
|
|
*/
|
2004-02-12 00:47:09 +00:00
|
|
|
int fpga_done_fn (int cookie)
|
2002-11-03 00:24:07 +00:00
|
|
|
{
|
2008-10-16 13:01:15 +00:00
|
|
|
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
|
2002-11-03 00:24:07 +00:00
|
|
|
|
2004-02-12 00:47:09 +00:00
|
|
|
PRINTF ("%s:%d: DONE check... ", __FUNCTION__, __LINE__);
|
2002-11-03 00:24:07 +00:00
|
|
|
if (immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_DONE_BIT_NUM)) {
|
2004-02-12 00:47:09 +00:00
|
|
|
PRINTF ("high\n");
|
2002-11-03 00:24:07 +00:00
|
|
|
return FPGA_SUCCESS;
|
2004-02-12 00:47:09 +00:00
|
|
|
} else {
|
|
|
|
PRINTF ("low\n");
|
2002-11-03 00:24:07 +00:00
|
|
|
return FPGA_FAIL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Read FPGA SelectMap data.
|
|
|
|
*/
|
2004-02-12 00:47:09 +00:00
|
|
|
int fpga_read_data_fn (unsigned char *data, int cookie)
|
2002-11-03 00:24:07 +00:00
|
|
|
{
|
2004-02-12 00:47:09 +00:00
|
|
|
vu_char *p = (vu_char *) SELECTMAP_BASE;
|
2002-11-03 00:24:07 +00:00
|
|
|
|
|
|
|
*data = *p;
|
|
|
|
#if 0
|
2004-02-12 00:47:09 +00:00
|
|
|
PRINTF ("%s: Read 0x%x into 0x%p\n", __FUNCTION__, (int) data, data);
|
2002-11-03 00:24:07 +00:00
|
|
|
#endif
|
2004-02-12 00:47:09 +00:00
|
|
|
return (int) data;
|
2002-11-03 00:24:07 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Write data to the FPGA SelectMap port
|
|
|
|
*/
|
2004-02-12 00:47:09 +00:00
|
|
|
int fpga_write_data_fn (unsigned char data, int flush, int cookie)
|
2002-11-03 00:24:07 +00:00
|
|
|
{
|
2004-02-12 00:47:09 +00:00
|
|
|
vu_char *p = (vu_char *) SELECTMAP_BASE;
|
2002-11-03 00:24:07 +00:00
|
|
|
|
|
|
|
#if 0
|
2004-02-12 00:47:09 +00:00
|
|
|
PRINTF ("%s: Write Data 0x%x\n", __FUNCTION__, (int) data);
|
2002-11-03 00:24:07 +00:00
|
|
|
#endif
|
|
|
|
*p = data;
|
2004-02-12 00:47:09 +00:00
|
|
|
return (int) data;
|
2002-11-03 00:24:07 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Abort and FPGA operation
|
|
|
|
*/
|
2004-02-12 00:47:09 +00:00
|
|
|
int fpga_abort_fn (int cookie)
|
2002-11-03 00:24:07 +00:00
|
|
|
{
|
2004-02-12 00:47:09 +00:00
|
|
|
PRINTF ("%s:%d: FPGA program sequence aborted\n",
|
|
|
|
__FUNCTION__, __LINE__);
|
2002-11-03 00:24:07 +00:00
|
|
|
return FPGA_FAIL;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* FPGA pre-configuration function. Just make sure that
|
|
|
|
* FPGA reset is asserted to keep the FPGA from starting up after
|
|
|
|
* configuration.
|
|
|
|
*/
|
2004-02-12 00:47:09 +00:00
|
|
|
int fpga_pre_config_fn (int cookie)
|
2002-11-03 00:24:07 +00:00
|
|
|
{
|
2004-02-12 00:47:09 +00:00
|
|
|
PRINTF ("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
|
2013-04-01 18:29:11 +00:00
|
|
|
fpga_reset(true);
|
2002-11-03 00:24:07 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* FPGA post configuration function. Blip the FPGA reset line and then see if
|
|
|
|
* the FPGA appears to be running.
|
|
|
|
*/
|
2004-02-12 00:47:09 +00:00
|
|
|
int fpga_post_config_fn (int cookie)
|
2002-11-03 00:24:07 +00:00
|
|
|
{
|
|
|
|
int rc;
|
|
|
|
|
2004-02-12 00:47:09 +00:00
|
|
|
PRINTF ("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__);
|
2013-04-01 18:29:11 +00:00
|
|
|
fpga_reset(true);
|
2004-02-12 00:47:09 +00:00
|
|
|
udelay (1000);
|
2013-04-01 18:29:11 +00:00
|
|
|
fpga_reset(false);
|
2002-11-03 00:24:07 +00:00
|
|
|
udelay (1000);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Use the FPGA,s inverting bus test register to do a simple test of the
|
|
|
|
* processor interface.
|
|
|
|
*/
|
2004-02-12 00:47:09 +00:00
|
|
|
rc = test_fpga_ibtr ();
|
2002-11-03 00:24:07 +00:00
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Clock, chip select and write signal assert functions and error check
|
|
|
|
* and busy functions. These are only stubs because the GEN860T selectmap
|
|
|
|
* interface handles sequencing of control signals automatically (it uses
|
|
|
|
* a memory-mapped interface to the FPGA SelectMap port). The design of
|
|
|
|
* the interface guarantees that the SelectMap port cannot be overrun so
|
|
|
|
* no busy check is needed. A configuration error is signalled by INIT
|
|
|
|
* going low during configuration, so there is no need for a separate error
|
|
|
|
* function.
|
|
|
|
*/
|
2004-02-12 00:47:09 +00:00
|
|
|
int fpga_clk_fn (int assert_clk, int flush, int cookie)
|
2002-11-03 00:24:07 +00:00
|
|
|
{
|
|
|
|
return assert_clk;
|
|
|
|
}
|
|
|
|
|
2004-02-12 00:47:09 +00:00
|
|
|
int fpga_cs_fn (int assert_cs, int flush, int cookie)
|
2002-11-03 00:24:07 +00:00
|
|
|
{
|
|
|
|
return assert_cs;
|
|
|
|
}
|
|
|
|
|
2004-02-12 00:47:09 +00:00
|
|
|
int fpga_wr_fn (int assert_write, int flush, int cookie)
|
2002-11-03 00:24:07 +00:00
|
|
|
{
|
|
|
|
return assert_write;
|
|
|
|
}
|
|
|
|
|
2004-02-12 00:47:09 +00:00
|
|
|
int fpga_err_fn (int cookie)
|
2002-11-03 00:24:07 +00:00
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2004-02-12 00:47:09 +00:00
|
|
|
int fpga_busy_fn (int cookie)
|
2002-11-03 00:24:07 +00:00
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif
|