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u-boot/configs/LicheePi_Zero_defconfig

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sunxi: add support for Lichee Pi Zero Lichee Pi Zero is a development board with a V3s SoC, which features 64MiB DRAM co-packaged within the SoC, a TF slot, a SPI NOR slot (not soldered in production batch), a 40-pin RGB LCD connector and some extra pins available as 2.54mm pins or stamp holes. Add support for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-08 07:30:14 +00:00
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
configs: Migrate CONFIG_SYS_TEXT_BASE On the NIOS2 and Xtensa architectures, we do not have CONFIG_SYS_TEXT_BASE set. This is a strict migration of the current values into the defconfig and removing them from the headers. I did not attempt to add more default values in and for now will leave that to maintainers. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-02-03 17:10:38 +00:00
CONFIG_SYS_TEXT_BASE=0x42e00000
sunxi: add support for Lichee Pi Zero Lichee Pi Zero is a development board with a V3s SoC, which features 64MiB DRAM co-packaged within the SoC, a TF slot, a SPI NOR slot (not soldered in production batch), a 40-pin RGB LCD connector and some extra pins available as 2.54mm pins or stamp holes. Add support for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-08 07:30:14 +00:00
CONFIG_MACH_SUN8I_V3S=y
CONFIG_DRAM_CLK=360
CONFIG_DRAM_ZQ=14779
CONFIG_DEFAULT_DEVICE_TREE="sun8i-v3s-licheepi-zero"
sunxi: defaultly enable SPL for Lichee Pi Zero As we have already DRAM initialization code for V3s SoC, we can defaultly enable SPL now on Lichee Pi Zero. Add CONFIG_SPL in Lichee Pi Zero defconfig. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-14 15:00:11 +00:00
CONFIG_SPL=y
sunxi: add support for Lichee Pi Zero Lichee Pi Zero is a development board with a V3s SoC, which features 64MiB DRAM co-packaged within the SoC, a TF slot, a SPI NOR slot (not soldered in production batch), a 40-pin RGB LCD connector and some extra pins available as 2.54mm pins or stamp holes. Add support for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-08 07:30:14 +00:00
# CONFIG_CMD_FLASH is not set
sunxi: defaultly enable SPL for Lichee Pi Zero As we have already DRAM initialization code for V3s SoC, we can defaultly enable SPL now on Lichee Pi Zero. Add CONFIG_SPL in Lichee Pi Zero defconfig. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-08-14 15:00:11 +00:00
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-17 01:35:43 +00:00
# CONFIG_NETDEVICES is not set
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
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