u-boot/arch/arm/dts/rk3399-puma.dtsi

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
dts: rk3399-puma: add DTS for RK3399-Q7 (Puma) SoM The RK3399-Q7 is a system-on-module featuring the Rockchip RK3399 in a Qseven-compatible form-factor. These changes add a device-tree describing the board and its interfaces for basic functionality (e.g. GbE, SPI, eMMC, SD-card). This includes the following changes from the original development: * dts: rk3399-puma: include DTS for RK3399-Q7 SoM in the Makefile * dts: rk3399-puma: add gmac for the RK3399-Q7 This change enables the Gigabit Ethernet support on the RK3399-Q7. * dts: rk3399-puma: use serial0 for stdout * dts: rk3399-puma: prepare the sdmmc node for SPL booting * dts: rk3399-puma: enable spi1 and spi5, add /spi1/spiflash The RK3399-Q7 (Puma) unsually (this is a build-time option for customised boards) has an on-module SPI-flash connected to SPI1. As of today, this is a Winbond W25Q32DW (32MBit) device. The SPI5 controller is routed to the Q7 edge connector and provides general-purpose SPI connectivity for customer base-boards. With some minor improvements on integration into our outbound tree - explicitly modelled the SPI flash as 'spiflash' under spi0 [dts: rk3399-puma: explicitly model spi-flash under spi1] - renamed the aliases to spi0 and spi1 to allow easier use of commands and legacy (SPL) infrastructure... i.e. the controllers will be 0 and 1 for 'sf probe', 'sspi', etc. [dts: rk3399-puma: rename aliases to number spi as 0 and 1 for commands] * dts: rk3399-puma: include SPI in the spl-boot-order property Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-03-28 16:48:51 +00:00
/*
* Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
dts: rk3399-puma: add DTS for RK3399-Q7 (Puma) SoM The RK3399-Q7 is a system-on-module featuring the Rockchip RK3399 in a Qseven-compatible form-factor. These changes add a device-tree describing the board and its interfaces for basic functionality (e.g. GbE, SPI, eMMC, SD-card). This includes the following changes from the original development: * dts: rk3399-puma: include DTS for RK3399-Q7 SoM in the Makefile * dts: rk3399-puma: add gmac for the RK3399-Q7 This change enables the Gigabit Ethernet support on the RK3399-Q7. * dts: rk3399-puma: use serial0 for stdout * dts: rk3399-puma: prepare the sdmmc node for SPL booting * dts: rk3399-puma: enable spi1 and spi5, add /spi1/spiflash The RK3399-Q7 (Puma) unsually (this is a build-time option for customised boards) has an on-module SPI-flash connected to SPI1. As of today, this is a Winbond W25Q32DW (32MBit) device. The SPI5 controller is routed to the Q7 edge connector and provides general-purpose SPI connectivity for customer base-boards. With some minor improvements on integration into our outbound tree - explicitly modelled the SPI flash as 'spiflash' under spi0 [dts: rk3399-puma: explicitly model spi-flash under spi1] - renamed the aliases to spi0 and spi1 to allow easier use of commands and legacy (SPL) infrastructure... i.e. the controllers will be 0 and 1 for 'sf probe', 'sspi', etc. [dts: rk3399-puma: rename aliases to number spi as 0 and 1 for commands] * dts: rk3399-puma: include SPI in the spl-boot-order property Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-03-28 16:48:51 +00:00
*/
#include <dt-bindings/pwm/pwm.h>
#include "rk3399.dtsi"
#include "rk3399-opp.dtsi"
dts: rk3399-puma: add DTS for RK3399-Q7 (Puma) SoM The RK3399-Q7 is a system-on-module featuring the Rockchip RK3399 in a Qseven-compatible form-factor. These changes add a device-tree describing the board and its interfaces for basic functionality (e.g. GbE, SPI, eMMC, SD-card). This includes the following changes from the original development: * dts: rk3399-puma: include DTS for RK3399-Q7 SoM in the Makefile * dts: rk3399-puma: add gmac for the RK3399-Q7 This change enables the Gigabit Ethernet support on the RK3399-Q7. * dts: rk3399-puma: use serial0 for stdout * dts: rk3399-puma: prepare the sdmmc node for SPL booting * dts: rk3399-puma: enable spi1 and spi5, add /spi1/spiflash The RK3399-Q7 (Puma) unsually (this is a build-time option for customised boards) has an on-module SPI-flash connected to SPI1. As of today, this is a Winbond W25Q32DW (32MBit) device. The SPI5 controller is routed to the Q7 edge connector and provides general-purpose SPI connectivity for customer base-boards. With some minor improvements on integration into our outbound tree - explicitly modelled the SPI flash as 'spiflash' under spi0 [dts: rk3399-puma: explicitly model spi-flash under spi1] - renamed the aliases to spi0 and spi1 to allow easier use of commands and legacy (SPL) infrastructure... i.e. the controllers will be 0 and 1 for 'sf probe', 'sspi', etc. [dts: rk3399-puma: rename aliases to number spi as 0 and 1 for commands] * dts: rk3399-puma: include SPI in the spl-boot-order property Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-03-28 16:48:51 +00:00
/ {
aliases {
mmc0 = &sdhci;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&module_led_pin>;
module_led: led-0 {
label = "module_led";
gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
panic-indicator;
};
};
extcon_usb3: extcon-usb3 {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb3_id>;
};
clkin_gmac: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "clkin_gmac";
#clock-cells = <0>;
};
vcc1v2_phy: vcc1v2-phy {
compatible = "regulator-fixed";
regulator-name = "vcc1v2_phy";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
vin-supply = <&vcc5v0_sys>;
dts: rk3399-puma: add DTS for RK3399-Q7 (Puma) SoM The RK3399-Q7 is a system-on-module featuring the Rockchip RK3399 in a Qseven-compatible form-factor. These changes add a device-tree describing the board and its interfaces for basic functionality (e.g. GbE, SPI, eMMC, SD-card). This includes the following changes from the original development: * dts: rk3399-puma: include DTS for RK3399-Q7 SoM in the Makefile * dts: rk3399-puma: add gmac for the RK3399-Q7 This change enables the Gigabit Ethernet support on the RK3399-Q7. * dts: rk3399-puma: use serial0 for stdout * dts: rk3399-puma: prepare the sdmmc node for SPL booting * dts: rk3399-puma: enable spi1 and spi5, add /spi1/spiflash The RK3399-Q7 (Puma) unsually (this is a build-time option for customised boards) has an on-module SPI-flash connected to SPI1. As of today, this is a Winbond W25Q32DW (32MBit) device. The SPI5 controller is routed to the Q7 edge connector and provides general-purpose SPI connectivity for customer base-boards. With some minor improvements on integration into our outbound tree - explicitly modelled the SPI flash as 'spiflash' under spi0 [dts: rk3399-puma: explicitly model spi-flash under spi1] - renamed the aliases to spi0 and spi1 to allow easier use of commands and legacy (SPL) infrastructure... i.e. the controllers will be 0 and 1 for 'sf probe', 'sspi', etc. [dts: rk3399-puma: rename aliases to number spi as 0 and 1 for commands] * dts: rk3399-puma: include SPI in the spl-boot-order property Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-03-28 16:48:51 +00:00
};
vcc3v3_sys: vcc3v3-sys {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc5v0_sys>;
dts: rk3399-puma: add DTS for RK3399-Q7 (Puma) SoM The RK3399-Q7 is a system-on-module featuring the Rockchip RK3399 in a Qseven-compatible form-factor. These changes add a device-tree describing the board and its interfaces for basic functionality (e.g. GbE, SPI, eMMC, SD-card). This includes the following changes from the original development: * dts: rk3399-puma: include DTS for RK3399-Q7 SoM in the Makefile * dts: rk3399-puma: add gmac for the RK3399-Q7 This change enables the Gigabit Ethernet support on the RK3399-Q7. * dts: rk3399-puma: use serial0 for stdout * dts: rk3399-puma: prepare the sdmmc node for SPL booting * dts: rk3399-puma: enable spi1 and spi5, add /spi1/spiflash The RK3399-Q7 (Puma) unsually (this is a build-time option for customised boards) has an on-module SPI-flash connected to SPI1. As of today, this is a Winbond W25Q32DW (32MBit) device. The SPI5 controller is routed to the Q7 edge connector and provides general-purpose SPI connectivity for customer base-boards. With some minor improvements on integration into our outbound tree - explicitly modelled the SPI flash as 'spiflash' under spi0 [dts: rk3399-puma: explicitly model spi-flash under spi1] - renamed the aliases to spi0 and spi1 to allow easier use of commands and legacy (SPL) infrastructure... i.e. the controllers will be 0 and 1 for 'sf probe', 'sspi', etc. [dts: rk3399-puma: rename aliases to number spi as 0 and 1 for commands] * dts: rk3399-puma: include SPI in the spl-boot-order property Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-03-28 16:48:51 +00:00
};
vcc5v0_host: vcc5v0-host-regulator {
dts: rk3399-puma: add DTS for RK3399-Q7 (Puma) SoM The RK3399-Q7 is a system-on-module featuring the Rockchip RK3399 in a Qseven-compatible form-factor. These changes add a device-tree describing the board and its interfaces for basic functionality (e.g. GbE, SPI, eMMC, SD-card). This includes the following changes from the original development: * dts: rk3399-puma: include DTS for RK3399-Q7 SoM in the Makefile * dts: rk3399-puma: add gmac for the RK3399-Q7 This change enables the Gigabit Ethernet support on the RK3399-Q7. * dts: rk3399-puma: use serial0 for stdout * dts: rk3399-puma: prepare the sdmmc node for SPL booting * dts: rk3399-puma: enable spi1 and spi5, add /spi1/spiflash The RK3399-Q7 (Puma) unsually (this is a build-time option for customised boards) has an on-module SPI-flash connected to SPI1. As of today, this is a Winbond W25Q32DW (32MBit) device. The SPI5 controller is routed to the Q7 edge connector and provides general-purpose SPI connectivity for customer base-boards. With some minor improvements on integration into our outbound tree - explicitly modelled the SPI flash as 'spiflash' under spi0 [dts: rk3399-puma: explicitly model spi-flash under spi1] - renamed the aliases to spi0 and spi1 to allow easier use of commands and legacy (SPL) infrastructure... i.e. the controllers will be 0 and 1 for 'sf probe', 'sspi', etc. [dts: rk3399-puma: rename aliases to number spi as 0 and 1 for commands] * dts: rk3399-puma: include SPI in the spl-boot-order property Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-03-28 16:48:51 +00:00
compatible = "regulator-fixed";
gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host_en>;
regulator-name = "vcc5v0_host";
dts: rk3399-puma: add DTS for RK3399-Q7 (Puma) SoM The RK3399-Q7 is a system-on-module featuring the Rockchip RK3399 in a Qseven-compatible form-factor. These changes add a device-tree describing the board and its interfaces for basic functionality (e.g. GbE, SPI, eMMC, SD-card). This includes the following changes from the original development: * dts: rk3399-puma: include DTS for RK3399-Q7 SoM in the Makefile * dts: rk3399-puma: add gmac for the RK3399-Q7 This change enables the Gigabit Ethernet support on the RK3399-Q7. * dts: rk3399-puma: use serial0 for stdout * dts: rk3399-puma: prepare the sdmmc node for SPL booting * dts: rk3399-puma: enable spi1 and spi5, add /spi1/spiflash The RK3399-Q7 (Puma) unsually (this is a build-time option for customised boards) has an on-module SPI-flash connected to SPI1. As of today, this is a Winbond W25Q32DW (32MBit) device. The SPI5 controller is routed to the Q7 edge connector and provides general-purpose SPI connectivity for customer base-boards. With some minor improvements on integration into our outbound tree - explicitly modelled the SPI flash as 'spiflash' under spi0 [dts: rk3399-puma: explicitly model spi-flash under spi1] - renamed the aliases to spi0 and spi1 to allow easier use of commands and legacy (SPL) infrastructure... i.e. the controllers will be 0 and 1 for 'sf probe', 'sspi', etc. [dts: rk3399-puma: rename aliases to number spi as 0 and 1 for commands] * dts: rk3399-puma: include SPI in the spl-boot-order property Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-03-28 16:48:51 +00:00
regulator-always-on;
vin-supply = <&vcc5v0_sys>;
dts: rk3399-puma: add DTS for RK3399-Q7 (Puma) SoM The RK3399-Q7 is a system-on-module featuring the Rockchip RK3399 in a Qseven-compatible form-factor. These changes add a device-tree describing the board and its interfaces for basic functionality (e.g. GbE, SPI, eMMC, SD-card). This includes the following changes from the original development: * dts: rk3399-puma: include DTS for RK3399-Q7 SoM in the Makefile * dts: rk3399-puma: add gmac for the RK3399-Q7 This change enables the Gigabit Ethernet support on the RK3399-Q7. * dts: rk3399-puma: use serial0 for stdout * dts: rk3399-puma: prepare the sdmmc node for SPL booting * dts: rk3399-puma: enable spi1 and spi5, add /spi1/spiflash The RK3399-Q7 (Puma) unsually (this is a build-time option for customised boards) has an on-module SPI-flash connected to SPI1. As of today, this is a Winbond W25Q32DW (32MBit) device. The SPI5 controller is routed to the Q7 edge connector and provides general-purpose SPI connectivity for customer base-boards. With some minor improvements on integration into our outbound tree - explicitly modelled the SPI flash as 'spiflash' under spi0 [dts: rk3399-puma: explicitly model spi-flash under spi1] - renamed the aliases to spi0 and spi1 to allow easier use of commands and legacy (SPL) infrastructure... i.e. the controllers will be 0 and 1 for 'sf probe', 'sspi', etc. [dts: rk3399-puma: rename aliases to number spi as 0 and 1 for commands] * dts: rk3399-puma: include SPI in the spl-boot-order property Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-03-28 16:48:51 +00:00
};
vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
dts: rk3399-puma: add DTS for RK3399-Q7 (Puma) SoM The RK3399-Q7 is a system-on-module featuring the Rockchip RK3399 in a Qseven-compatible form-factor. These changes add a device-tree describing the board and its interfaces for basic functionality (e.g. GbE, SPI, eMMC, SD-card). This includes the following changes from the original development: * dts: rk3399-puma: include DTS for RK3399-Q7 SoM in the Makefile * dts: rk3399-puma: add gmac for the RK3399-Q7 This change enables the Gigabit Ethernet support on the RK3399-Q7. * dts: rk3399-puma: use serial0 for stdout * dts: rk3399-puma: prepare the sdmmc node for SPL booting * dts: rk3399-puma: enable spi1 and spi5, add /spi1/spiflash The RK3399-Q7 (Puma) unsually (this is a build-time option for customised boards) has an on-module SPI-flash connected to SPI1. As of today, this is a Winbond W25Q32DW (32MBit) device. The SPI5 controller is routed to the Q7 edge connector and provides general-purpose SPI connectivity for customer base-boards. With some minor improvements on integration into our outbound tree - explicitly modelled the SPI flash as 'spiflash' under spi0 [dts: rk3399-puma: explicitly model spi-flash under spi1] - renamed the aliases to spi0 and spi1 to allow easier use of commands and legacy (SPL) infrastructure... i.e. the controllers will be 0 and 1 for 'sf probe', 'sspi', etc. [dts: rk3399-puma: rename aliases to number spi as 0 and 1 for commands] * dts: rk3399-puma: include SPI in the spl-boot-order property Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-03-28 16:48:51 +00:00
};
vdd_log: vdd-log {
compatible = "pwm-regulator";
pwms = <&pwm2 0 25000 1>;
pwm-supply = <&vcc5v0_sys>;
regulator-name = "vdd_log";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-always-on;
regulator-boot-on;
};
};
dts: rk3399-puma: add DTS for RK3399-Q7 (Puma) SoM The RK3399-Q7 is a system-on-module featuring the Rockchip RK3399 in a Qseven-compatible form-factor. These changes add a device-tree describing the board and its interfaces for basic functionality (e.g. GbE, SPI, eMMC, SD-card). This includes the following changes from the original development: * dts: rk3399-puma: include DTS for RK3399-Q7 SoM in the Makefile * dts: rk3399-puma: add gmac for the RK3399-Q7 This change enables the Gigabit Ethernet support on the RK3399-Q7. * dts: rk3399-puma: use serial0 for stdout * dts: rk3399-puma: prepare the sdmmc node for SPL booting * dts: rk3399-puma: enable spi1 and spi5, add /spi1/spiflash The RK3399-Q7 (Puma) unsually (this is a build-time option for customised boards) has an on-module SPI-flash connected to SPI1. As of today, this is a Winbond W25Q32DW (32MBit) device. The SPI5 controller is routed to the Q7 edge connector and provides general-purpose SPI connectivity for customer base-boards. With some minor improvements on integration into our outbound tree - explicitly modelled the SPI flash as 'spiflash' under spi0 [dts: rk3399-puma: explicitly model spi-flash under spi1] - renamed the aliases to spi0 and spi1 to allow easier use of commands and legacy (SPL) infrastructure... i.e. the controllers will be 0 and 1 for 'sf probe', 'sspi', etc. [dts: rk3399-puma: rename aliases to number spi as 0 and 1 for commands] * dts: rk3399-puma: include SPI in the spl-boot-order property Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-03-28 16:48:51 +00:00
&cpu_b0 {
cpu-supply = <&vdd_cpu_b>;
};
&cpu_b1 {
cpu-supply = <&vdd_cpu_b>;
};
&cpu_l0 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l1 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l2 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l3 {
cpu-supply = <&vdd_cpu_l>;
dts: rk3399-puma: add DTS for RK3399-Q7 (Puma) SoM The RK3399-Q7 is a system-on-module featuring the Rockchip RK3399 in a Qseven-compatible form-factor. These changes add a device-tree describing the board and its interfaces for basic functionality (e.g. GbE, SPI, eMMC, SD-card). This includes the following changes from the original development: * dts: rk3399-puma: include DTS for RK3399-Q7 SoM in the Makefile * dts: rk3399-puma: add gmac for the RK3399-Q7 This change enables the Gigabit Ethernet support on the RK3399-Q7. * dts: rk3399-puma: use serial0 for stdout * dts: rk3399-puma: prepare the sdmmc node for SPL booting * dts: rk3399-puma: enable spi1 and spi5, add /spi1/spiflash The RK3399-Q7 (Puma) unsually (this is a build-time option for customised boards) has an on-module SPI-flash connected to SPI1. As of today, this is a Winbond W25Q32DW (32MBit) device. The SPI5 controller is routed to the Q7 edge connector and provides general-purpose SPI connectivity for customer base-boards. With some minor improvements on integration into our outbound tree - explicitly modelled the SPI flash as 'spiflash' under spi0 [dts: rk3399-puma: explicitly model spi-flash under spi1] - renamed the aliases to spi0 and spi1 to allow easier use of commands and legacy (SPL) infrastructure... i.e. the controllers will be 0 and 1 for 'sf probe', 'sspi', etc. [dts: rk3399-puma: rename aliases to number spi as 0 and 1 for commands] * dts: rk3399-puma: include SPI in the spl-boot-order property Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-03-28 16:48:51 +00:00
};
&emmc_phy {
status = "okay";
drive-impedance-ohm = <33>;
dts: rk3399-puma: add DTS for RK3399-Q7 (Puma) SoM The RK3399-Q7 is a system-on-module featuring the Rockchip RK3399 in a Qseven-compatible form-factor. These changes add a device-tree describing the board and its interfaces for basic functionality (e.g. GbE, SPI, eMMC, SD-card). This includes the following changes from the original development: * dts: rk3399-puma: include DTS for RK3399-Q7 SoM in the Makefile * dts: rk3399-puma: add gmac for the RK3399-Q7 This change enables the Gigabit Ethernet support on the RK3399-Q7. * dts: rk3399-puma: use serial0 for stdout * dts: rk3399-puma: prepare the sdmmc node for SPL booting * dts: rk3399-puma: enable spi1 and spi5, add /spi1/spiflash The RK3399-Q7 (Puma) unsually (this is a build-time option for customised boards) has an on-module SPI-flash connected to SPI1. As of today, this is a Winbond W25Q32DW (32MBit) device. The SPI5 controller is routed to the Q7 edge connector and provides general-purpose SPI connectivity for customer base-boards. With some minor improvements on integration into our outbound tree - explicitly modelled the SPI flash as 'spiflash' under spi0 [dts: rk3399-puma: explicitly model spi-flash under spi1] - renamed the aliases to spi0 and spi1 to allow easier use of commands and legacy (SPL) infrastructure... i.e. the controllers will be 0 and 1 for 'sf probe', 'sspi', etc. [dts: rk3399-puma: rename aliases to number spi as 0 and 1 for commands] * dts: rk3399-puma: include SPI in the spl-boot-order property Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-03-28 16:48:51 +00:00
};
&gmac {
assigned-clocks = <&cru SCLK_RMII_SRC>;
assigned-clock-parents = <&clkin_gmac>;
clock_in_out = "input";
phy-supply = <&vcc1v2_phy>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
snps,reset-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
tx_delay = <0x10>;
rx_delay = <0x10>;
dts: rk3399-puma: add DTS for RK3399-Q7 (Puma) SoM The RK3399-Q7 is a system-on-module featuring the Rockchip RK3399 in a Qseven-compatible form-factor. These changes add a device-tree describing the board and its interfaces for basic functionality (e.g. GbE, SPI, eMMC, SD-card). This includes the following changes from the original development: * dts: rk3399-puma: include DTS for RK3399-Q7 SoM in the Makefile * dts: rk3399-puma: add gmac for the RK3399-Q7 This change enables the Gigabit Ethernet support on the RK3399-Q7. * dts: rk3399-puma: use serial0 for stdout * dts: rk3399-puma: prepare the sdmmc node for SPL booting * dts: rk3399-puma: enable spi1 and spi5, add /spi1/spiflash The RK3399-Q7 (Puma) unsually (this is a build-time option for customised boards) has an on-module SPI-flash connected to SPI1. As of today, this is a Winbond W25Q32DW (32MBit) device. The SPI5 controller is routed to the Q7 edge connector and provides general-purpose SPI connectivity for customer base-boards. With some minor improvements on integration into our outbound tree - explicitly modelled the SPI flash as 'spiflash' under spi0 [dts: rk3399-puma: explicitly model spi-flash under spi1] - renamed the aliases to spi0 and spi1 to allow easier use of commands and legacy (SPL) infrastructure... i.e. the controllers will be 0 and 1 for 'sf probe', 'sspi', etc. [dts: rk3399-puma: rename aliases to number spi as 0 and 1 for commands] * dts: rk3399-puma: include SPI in the spl-boot-order property Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-03-28 16:48:51 +00:00
status = "okay";
};
&gpu {
mali-supply = <&vdd_gpu>;
dts: rk3399-puma: add DTS for RK3399-Q7 (Puma) SoM The RK3399-Q7 is a system-on-module featuring the Rockchip RK3399 in a Qseven-compatible form-factor. These changes add a device-tree describing the board and its interfaces for basic functionality (e.g. GbE, SPI, eMMC, SD-card). This includes the following changes from the original development: * dts: rk3399-puma: include DTS for RK3399-Q7 SoM in the Makefile * dts: rk3399-puma: add gmac for the RK3399-Q7 This change enables the Gigabit Ethernet support on the RK3399-Q7. * dts: rk3399-puma: use serial0 for stdout * dts: rk3399-puma: prepare the sdmmc node for SPL booting * dts: rk3399-puma: enable spi1 and spi5, add /spi1/spiflash The RK3399-Q7 (Puma) unsually (this is a build-time option for customised boards) has an on-module SPI-flash connected to SPI1. As of today, this is a Winbond W25Q32DW (32MBit) device. The SPI5 controller is routed to the Q7 edge connector and provides general-purpose SPI connectivity for customer base-boards. With some minor improvements on integration into our outbound tree - explicitly modelled the SPI flash as 'spiflash' under spi0 [dts: rk3399-puma: explicitly model spi-flash under spi1] - renamed the aliases to spi0 and spi1 to allow easier use of commands and legacy (SPL) infrastructure... i.e. the controllers will be 0 and 1 for 'sf probe', 'sspi', etc. [dts: rk3399-puma: rename aliases to number spi as 0 and 1 for commands] * dts: rk3399-puma: include SPI in the spl-boot-order property Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-03-28 16:48:51 +00:00
status = "okay";
};
&i2c0 {
dts: rk3399-puma: add DTS for RK3399-Q7 (Puma) SoM The RK3399-Q7 is a system-on-module featuring the Rockchip RK3399 in a Qseven-compatible form-factor. These changes add a device-tree describing the board and its interfaces for basic functionality (e.g. GbE, SPI, eMMC, SD-card). This includes the following changes from the original development: * dts: rk3399-puma: include DTS for RK3399-Q7 SoM in the Makefile * dts: rk3399-puma: add gmac for the RK3399-Q7 This change enables the Gigabit Ethernet support on the RK3399-Q7. * dts: rk3399-puma: use serial0 for stdout * dts: rk3399-puma: prepare the sdmmc node for SPL booting * dts: rk3399-puma: enable spi1 and spi5, add /spi1/spiflash The RK3399-Q7 (Puma) unsually (this is a build-time option for customised boards) has an on-module SPI-flash connected to SPI1. As of today, this is a Winbond W25Q32DW (32MBit) device. The SPI5 controller is routed to the Q7 edge connector and provides general-purpose SPI connectivity for customer base-boards. With some minor improvements on integration into our outbound tree - explicitly modelled the SPI flash as 'spiflash' under spi0 [dts: rk3399-puma: explicitly model spi-flash under spi1] - renamed the aliases to spi0 and spi1 to allow easier use of commands and legacy (SPL) infrastructure... i.e. the controllers will be 0 and 1 for 'sf probe', 'sspi', etc. [dts: rk3399-puma: rename aliases to number spi as 0 and 1 for commands] * dts: rk3399-puma: include SPI in the spl-boot-order property Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-03-28 16:48:51 +00:00
status = "okay";
i2c-scl-rising-time-ns = <168>;
i2c-scl-falling-time-ns = <4>;
clock-frequency = <400000>;
rk808: pmic@1b {
compatible = "rockchip,rk808";
reg = <0x1b>;
interrupt-parent = <&gpio1>;
interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk808-clkout2";
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
rockchip,system-power-controller;
wakeup-source;
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
vcc3-supply = <&vcc5v0_sys>;
vcc4-supply = <&vcc5v0_sys>;
vcc6-supply = <&vcc5v0_sys>;
vcc7-supply = <&vcc5v0_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc5v0_sys>;
vcc10-supply = <&vcc5v0_sys>;
vcc11-supply = <&vcc5v0_sys>;
vcc12-supply = <&vcc3v3_sys>;
vddio-supply = <&vcc1v8_pmu>;
regulators {
vdd_center: DCDC_REG1 {
regulator-name = "vdd_center";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_cpu_l: DCDC_REG2 {
regulator-name = "vdd_cpu_l";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_1v8: DCDC_REG4 {
regulator-name = "vcc_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc_ldo1: LDO_REG1 {
regulator-name = "vcc_ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc1v8_hdmi: LDO_REG2 {
regulator-name = "vcc1v8_hdmi";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc1v8_pmu: LDO_REG3 {
regulator-name = "vcc1v8_pmu";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc_sd: LDO_REG4 {
regulator-name = "vcc_sd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vcc_ldo5: LDO_REG5 {
regulator-name = "vcc_ldo5";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ldo6: LDO_REG6 {
regulator-name = "vcc_ldo6";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc0v9_hdmi: LDO_REG7 {
regulator-name = "vcc0v9_hdmi";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_efuse: LDO_REG8 {
regulator-name = "vcc_efuse";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_s3: SWITCH_REG1 {
regulator-name = "vcc3v3_s3";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_s0: SWITCH_REG2 {
regulator-name = "vcc3v3_s0";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
vdd_gpu: regulator@60 {
compatible = "fcs,fan53555";
reg = <0x60>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_gpu";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1230000>;
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
};
};
&i2c7 {
status = "okay";
clock-frequency = <400000>;
fan: fan@18 {
compatible = "ti,amc6821";
reg = <0x18>;
#cooling-cells = <2>;
};
rtc_twi: rtc@6f {
compatible = "isil,isl1208";
reg = <0x6f>;
};
dts: rk3399-puma: add DTS for RK3399-Q7 (Puma) SoM The RK3399-Q7 is a system-on-module featuring the Rockchip RK3399 in a Qseven-compatible form-factor. These changes add a device-tree describing the board and its interfaces for basic functionality (e.g. GbE, SPI, eMMC, SD-card). This includes the following changes from the original development: * dts: rk3399-puma: include DTS for RK3399-Q7 SoM in the Makefile * dts: rk3399-puma: add gmac for the RK3399-Q7 This change enables the Gigabit Ethernet support on the RK3399-Q7. * dts: rk3399-puma: use serial0 for stdout * dts: rk3399-puma: prepare the sdmmc node for SPL booting * dts: rk3399-puma: enable spi1 and spi5, add /spi1/spiflash The RK3399-Q7 (Puma) unsually (this is a build-time option for customised boards) has an on-module SPI-flash connected to SPI1. As of today, this is a Winbond W25Q32DW (32MBit) device. The SPI5 controller is routed to the Q7 edge connector and provides general-purpose SPI connectivity for customer base-boards. With some minor improvements on integration into our outbound tree - explicitly modelled the SPI flash as 'spiflash' under spi0 [dts: rk3399-puma: explicitly model spi-flash under spi1] - renamed the aliases to spi0 and spi1 to allow easier use of commands and legacy (SPL) infrastructure... i.e. the controllers will be 0 and 1 for 'sf probe', 'sspi', etc. [dts: rk3399-puma: rename aliases to number spi as 0 and 1 for commands] * dts: rk3399-puma: include SPI in the spl-boot-order property Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-03-28 16:48:51 +00:00
};
&i2c8 {
status = "okay";
clock-frequency = <400000>;
vdd_cpu_b: regulator@60 {
compatible = "fcs,fan53555";
reg = <0x60>;
vin-supply = <&vcc5v0_sys>;
regulator-name = "vdd_cpu_b";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1230000>;
regulator-ramp-delay = <1000>;
fcs,suspend-voltage-selector = <1>;
regulator-always-on;
regulator-boot-on;
};
};
&i2s0 {
pinctrl-0 = <&i2s0_2ch_bus>;
rockchip,playback-channels = <2>;
rockchip,capture-channels = <2>;
status = "okay";
};
/*
* As Q7 does not specify neither a global nor a RX clock for I2S these
* signals are not used. Furthermore I2S0_LRCK_RX is used as GPIO.
* Therefore we have to redefine the i2s0_2ch_bus definition to prevent
* conflicts.
*/
&i2s0_2ch_bus {
rockchip,pins =
<3 RK_PD0 1 &pcfg_pull_none>,
<3 RK_PD2 1 &pcfg_pull_none>,
<3 RK_PD3 1 &pcfg_pull_none>,
<3 RK_PD7 1 &pcfg_pull_none>;
};
&io_domains {
status = "okay";
bt656-supply = <&vcc_1v8>;
audio-supply = <&vcc_1v8>;
sdmmc-supply = <&vcc_sd>;
gpio1830-supply = <&vcc_1v8>;
};
&pmu_io_domains {
status = "okay";
pmu1830-supply = <&vcc_1v8>;
};
&pwm2 {
dts: rk3399-puma: add DTS for RK3399-Q7 (Puma) SoM The RK3399-Q7 is a system-on-module featuring the Rockchip RK3399 in a Qseven-compatible form-factor. These changes add a device-tree describing the board and its interfaces for basic functionality (e.g. GbE, SPI, eMMC, SD-card). This includes the following changes from the original development: * dts: rk3399-puma: include DTS for RK3399-Q7 SoM in the Makefile * dts: rk3399-puma: add gmac for the RK3399-Q7 This change enables the Gigabit Ethernet support on the RK3399-Q7. * dts: rk3399-puma: use serial0 for stdout * dts: rk3399-puma: prepare the sdmmc node for SPL booting * dts: rk3399-puma: enable spi1 and spi5, add /spi1/spiflash The RK3399-Q7 (Puma) unsually (this is a build-time option for customised boards) has an on-module SPI-flash connected to SPI1. As of today, this is a Winbond W25Q32DW (32MBit) device. The SPI5 controller is routed to the Q7 edge connector and provides general-purpose SPI connectivity for customer base-boards. With some minor improvements on integration into our outbound tree - explicitly modelled the SPI flash as 'spiflash' under spi0 [dts: rk3399-puma: explicitly model spi-flash under spi1] - renamed the aliases to spi0 and spi1 to allow easier use of commands and legacy (SPL) infrastructure... i.e. the controllers will be 0 and 1 for 'sf probe', 'sspi', etc. [dts: rk3399-puma: rename aliases to number spi as 0 and 1 for commands] * dts: rk3399-puma: include SPI in the spl-boot-order property Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-03-28 16:48:51 +00:00
status = "okay";
};
&pinctrl {
i2c8 {
i2c8_xfer_a: i2c8-xfer {
rockchip,pins =
<1 RK_PC4 1 &pcfg_pull_up>,
<1 RK_PC5 1 &pcfg_pull_up>;
};
};
leds {
module_led_pin: module-led-pin {
dts: rk3399-puma: add DTS for RK3399-Q7 (Puma) SoM The RK3399-Q7 is a system-on-module featuring the Rockchip RK3399 in a Qseven-compatible form-factor. These changes add a device-tree describing the board and its interfaces for basic functionality (e.g. GbE, SPI, eMMC, SD-card). This includes the following changes from the original development: * dts: rk3399-puma: include DTS for RK3399-Q7 SoM in the Makefile * dts: rk3399-puma: add gmac for the RK3399-Q7 This change enables the Gigabit Ethernet support on the RK3399-Q7. * dts: rk3399-puma: use serial0 for stdout * dts: rk3399-puma: prepare the sdmmc node for SPL booting * dts: rk3399-puma: enable spi1 and spi5, add /spi1/spiflash The RK3399-Q7 (Puma) unsually (this is a build-time option for customised boards) has an on-module SPI-flash connected to SPI1. As of today, this is a Winbond W25Q32DW (32MBit) device. The SPI5 controller is routed to the Q7 edge connector and provides general-purpose SPI connectivity for customer base-boards. With some minor improvements on integration into our outbound tree - explicitly modelled the SPI flash as 'spiflash' under spi0 [dts: rk3399-puma: explicitly model spi-flash under spi1] - renamed the aliases to spi0 and spi1 to allow easier use of commands and legacy (SPL) infrastructure... i.e. the controllers will be 0 and 1 for 'sf probe', 'sspi', etc. [dts: rk3399-puma: rename aliases to number spi as 0 and 1 for commands] * dts: rk3399-puma: include SPI in the spl-boot-order property Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-03-28 16:48:51 +00:00
rockchip,pins =
<2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
dts: rk3399-puma: add DTS for RK3399-Q7 (Puma) SoM The RK3399-Q7 is a system-on-module featuring the Rockchip RK3399 in a Qseven-compatible form-factor. These changes add a device-tree describing the board and its interfaces for basic functionality (e.g. GbE, SPI, eMMC, SD-card). This includes the following changes from the original development: * dts: rk3399-puma: include DTS for RK3399-Q7 SoM in the Makefile * dts: rk3399-puma: add gmac for the RK3399-Q7 This change enables the Gigabit Ethernet support on the RK3399-Q7. * dts: rk3399-puma: use serial0 for stdout * dts: rk3399-puma: prepare the sdmmc node for SPL booting * dts: rk3399-puma: enable spi1 and spi5, add /spi1/spiflash The RK3399-Q7 (Puma) unsually (this is a build-time option for customised boards) has an on-module SPI-flash connected to SPI1. As of today, this is a Winbond W25Q32DW (32MBit) device. The SPI5 controller is routed to the Q7 edge connector and provides general-purpose SPI connectivity for customer base-boards. With some minor improvements on integration into our outbound tree - explicitly modelled the SPI flash as 'spiflash' under spi0 [dts: rk3399-puma: explicitly model spi-flash under spi1] - renamed the aliases to spi0 and spi1 to allow easier use of commands and legacy (SPL) infrastructure... i.e. the controllers will be 0 and 1 for 'sf probe', 'sspi', etc. [dts: rk3399-puma: rename aliases to number spi as 0 and 1 for commands] * dts: rk3399-puma: include SPI in the spl-boot-order property Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-03-28 16:48:51 +00:00
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins =
<1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
usb2 {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins =
<4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
dts: rk3399-puma: add DTS for RK3399-Q7 (Puma) SoM The RK3399-Q7 is a system-on-module featuring the Rockchip RK3399 in a Qseven-compatible form-factor. These changes add a device-tree describing the board and its interfaces for basic functionality (e.g. GbE, SPI, eMMC, SD-card). This includes the following changes from the original development: * dts: rk3399-puma: include DTS for RK3399-Q7 SoM in the Makefile * dts: rk3399-puma: add gmac for the RK3399-Q7 This change enables the Gigabit Ethernet support on the RK3399-Q7. * dts: rk3399-puma: use serial0 for stdout * dts: rk3399-puma: prepare the sdmmc node for SPL booting * dts: rk3399-puma: enable spi1 and spi5, add /spi1/spiflash The RK3399-Q7 (Puma) unsually (this is a build-time option for customised boards) has an on-module SPI-flash connected to SPI1. As of today, this is a Winbond W25Q32DW (32MBit) device. The SPI5 controller is routed to the Q7 edge connector and provides general-purpose SPI connectivity for customer base-boards. With some minor improvements on integration into our outbound tree - explicitly modelled the SPI flash as 'spiflash' under spi0 [dts: rk3399-puma: explicitly model spi-flash under spi1] - renamed the aliases to spi0 and spi1 to allow easier use of commands and legacy (SPL) infrastructure... i.e. the controllers will be 0 and 1 for 'sf probe', 'sspi', etc. [dts: rk3399-puma: rename aliases to number spi as 0 and 1 for commands] * dts: rk3399-puma: include SPI in the spl-boot-order property Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-03-28 16:48:51 +00:00
};
};
usb3 {
usb3_id: usb3-id {
rockchip,pins =
<1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
dts: rk3399-puma: add DTS for RK3399-Q7 (Puma) SoM The RK3399-Q7 is a system-on-module featuring the Rockchip RK3399 in a Qseven-compatible form-factor. These changes add a device-tree describing the board and its interfaces for basic functionality (e.g. GbE, SPI, eMMC, SD-card). This includes the following changes from the original development: * dts: rk3399-puma: include DTS for RK3399-Q7 SoM in the Makefile * dts: rk3399-puma: add gmac for the RK3399-Q7 This change enables the Gigabit Ethernet support on the RK3399-Q7. * dts: rk3399-puma: use serial0 for stdout * dts: rk3399-puma: prepare the sdmmc node for SPL booting * dts: rk3399-puma: enable spi1 and spi5, add /spi1/spiflash The RK3399-Q7 (Puma) unsually (this is a build-time option for customised boards) has an on-module SPI-flash connected to SPI1. As of today, this is a Winbond W25Q32DW (32MBit) device. The SPI5 controller is routed to the Q7 edge connector and provides general-purpose SPI connectivity for customer base-boards. With some minor improvements on integration into our outbound tree - explicitly modelled the SPI flash as 'spiflash' under spi0 [dts: rk3399-puma: explicitly model spi-flash under spi1] - renamed the aliases to spi0 and spi1 to allow easier use of commands and legacy (SPL) infrastructure... i.e. the controllers will be 0 and 1 for 'sf probe', 'sspi', etc. [dts: rk3399-puma: rename aliases to number spi as 0 and 1 for commands] * dts: rk3399-puma: include SPI in the spl-boot-order property Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-03-28 16:48:51 +00:00
};
&sdhci {
/*
* Signal integrity isn't great at 200MHz but 100MHz has proven stable
* enough.
*/
max-frequency = <100000000>;
bus-width = <8>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
non-removable;
status = "okay";
};
&sdmmc {
vqmmc-supply = <&vcc_sd>;
};
&spi1 {
status = "okay";
norflash: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
};
};
&tcphy1 {
status = "okay";
};
&tsadc {
rockchip,hw-tshut-mode = <1>;
rockchip,hw-tshut-polarity = <1>;
status = "okay";
};
&u2phy1 {
status = "okay";
u2phy1_otg: otg-port {
status = "okay";
};
u2phy1_host: host-port {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
};
&usbdrd3_1 {
dts: rk3399-puma: add DTS for RK3399-Q7 (Puma) SoM The RK3399-Q7 is a system-on-module featuring the Rockchip RK3399 in a Qseven-compatible form-factor. These changes add a device-tree describing the board and its interfaces for basic functionality (e.g. GbE, SPI, eMMC, SD-card). This includes the following changes from the original development: * dts: rk3399-puma: include DTS for RK3399-Q7 SoM in the Makefile * dts: rk3399-puma: add gmac for the RK3399-Q7 This change enables the Gigabit Ethernet support on the RK3399-Q7. * dts: rk3399-puma: use serial0 for stdout * dts: rk3399-puma: prepare the sdmmc node for SPL booting * dts: rk3399-puma: enable spi1 and spi5, add /spi1/spiflash The RK3399-Q7 (Puma) unsually (this is a build-time option for customised boards) has an on-module SPI-flash connected to SPI1. As of today, this is a Winbond W25Q32DW (32MBit) device. The SPI5 controller is routed to the Q7 edge connector and provides general-purpose SPI connectivity for customer base-boards. With some minor improvements on integration into our outbound tree - explicitly modelled the SPI flash as 'spiflash' under spi0 [dts: rk3399-puma: explicitly model spi-flash under spi1] - renamed the aliases to spi0 and spi1 to allow easier use of commands and legacy (SPL) infrastructure... i.e. the controllers will be 0 and 1 for 'sf probe', 'sspi', etc. [dts: rk3399-puma: rename aliases to number spi as 0 and 1 for commands] * dts: rk3399-puma: include SPI in the spl-boot-order property Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-03-28 16:48:51 +00:00
status = "okay";
};
&usbdrd_dwc3_1 {
dts: rk3399-puma: add DTS for RK3399-Q7 (Puma) SoM The RK3399-Q7 is a system-on-module featuring the Rockchip RK3399 in a Qseven-compatible form-factor. These changes add a device-tree describing the board and its interfaces for basic functionality (e.g. GbE, SPI, eMMC, SD-card). This includes the following changes from the original development: * dts: rk3399-puma: include DTS for RK3399-Q7 SoM in the Makefile * dts: rk3399-puma: add gmac for the RK3399-Q7 This change enables the Gigabit Ethernet support on the RK3399-Q7. * dts: rk3399-puma: use serial0 for stdout * dts: rk3399-puma: prepare the sdmmc node for SPL booting * dts: rk3399-puma: enable spi1 and spi5, add /spi1/spiflash The RK3399-Q7 (Puma) unsually (this is a build-time option for customised boards) has an on-module SPI-flash connected to SPI1. As of today, this is a Winbond W25Q32DW (32MBit) device. The SPI5 controller is routed to the Q7 edge connector and provides general-purpose SPI connectivity for customer base-boards. With some minor improvements on integration into our outbound tree - explicitly modelled the SPI flash as 'spiflash' under spi0 [dts: rk3399-puma: explicitly model spi-flash under spi1] - renamed the aliases to spi0 and spi1 to allow easier use of commands and legacy (SPL) infrastructure... i.e. the controllers will be 0 and 1 for 'sf probe', 'sspi', etc. [dts: rk3399-puma: rename aliases to number spi as 0 and 1 for commands] * dts: rk3399-puma: include SPI in the spl-boot-order property Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-03-28 16:48:51 +00:00
status = "okay";
dr_mode = "host";
};
dts: rk3399-puma: add DTS for RK3399-Q7 (Puma) SoM The RK3399-Q7 is a system-on-module featuring the Rockchip RK3399 in a Qseven-compatible form-factor. These changes add a device-tree describing the board and its interfaces for basic functionality (e.g. GbE, SPI, eMMC, SD-card). This includes the following changes from the original development: * dts: rk3399-puma: include DTS for RK3399-Q7 SoM in the Makefile * dts: rk3399-puma: add gmac for the RK3399-Q7 This change enables the Gigabit Ethernet support on the RK3399-Q7. * dts: rk3399-puma: use serial0 for stdout * dts: rk3399-puma: prepare the sdmmc node for SPL booting * dts: rk3399-puma: enable spi1 and spi5, add /spi1/spiflash The RK3399-Q7 (Puma) unsually (this is a build-time option for customised boards) has an on-module SPI-flash connected to SPI1. As of today, this is a Winbond W25Q32DW (32MBit) device. The SPI5 controller is routed to the Q7 edge connector and provides general-purpose SPI connectivity for customer base-boards. With some minor improvements on integration into our outbound tree - explicitly modelled the SPI flash as 'spiflash' under spi0 [dts: rk3399-puma: explicitly model spi-flash under spi1] - renamed the aliases to spi0 and spi1 to allow easier use of commands and legacy (SPL) infrastructure... i.e. the controllers will be 0 and 1 for 'sf probe', 'sspi', etc. [dts: rk3399-puma: rename aliases to number spi as 0 and 1 for commands] * dts: rk3399-puma: include SPI in the spl-boot-order property Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-03-28 16:48:51 +00:00
&usb_host1_ehci {
status = "okay";
dts: rk3399-puma: add DTS for RK3399-Q7 (Puma) SoM The RK3399-Q7 is a system-on-module featuring the Rockchip RK3399 in a Qseven-compatible form-factor. These changes add a device-tree describing the board and its interfaces for basic functionality (e.g. GbE, SPI, eMMC, SD-card). This includes the following changes from the original development: * dts: rk3399-puma: include DTS for RK3399-Q7 SoM in the Makefile * dts: rk3399-puma: add gmac for the RK3399-Q7 This change enables the Gigabit Ethernet support on the RK3399-Q7. * dts: rk3399-puma: use serial0 for stdout * dts: rk3399-puma: prepare the sdmmc node for SPL booting * dts: rk3399-puma: enable spi1 and spi5, add /spi1/spiflash The RK3399-Q7 (Puma) unsually (this is a build-time option for customised boards) has an on-module SPI-flash connected to SPI1. As of today, this is a Winbond W25Q32DW (32MBit) device. The SPI5 controller is routed to the Q7 edge connector and provides general-purpose SPI connectivity for customer base-boards. With some minor improvements on integration into our outbound tree - explicitly modelled the SPI flash as 'spiflash' under spi0 [dts: rk3399-puma: explicitly model spi-flash under spi1] - renamed the aliases to spi0 and spi1 to allow easier use of commands and legacy (SPL) infrastructure... i.e. the controllers will be 0 and 1 for 'sf probe', 'sspi', etc. [dts: rk3399-puma: rename aliases to number spi as 0 and 1 for commands] * dts: rk3399-puma: include SPI in the spl-boot-order property Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-03-28 16:48:51 +00:00
};
&usb_host1_ohci {
dts: rk3399-puma: add DTS for RK3399-Q7 (Puma) SoM The RK3399-Q7 is a system-on-module featuring the Rockchip RK3399 in a Qseven-compatible form-factor. These changes add a device-tree describing the board and its interfaces for basic functionality (e.g. GbE, SPI, eMMC, SD-card). This includes the following changes from the original development: * dts: rk3399-puma: include DTS for RK3399-Q7 SoM in the Makefile * dts: rk3399-puma: add gmac for the RK3399-Q7 This change enables the Gigabit Ethernet support on the RK3399-Q7. * dts: rk3399-puma: use serial0 for stdout * dts: rk3399-puma: prepare the sdmmc node for SPL booting * dts: rk3399-puma: enable spi1 and spi5, add /spi1/spiflash The RK3399-Q7 (Puma) unsually (this is a build-time option for customised boards) has an on-module SPI-flash connected to SPI1. As of today, this is a Winbond W25Q32DW (32MBit) device. The SPI5 controller is routed to the Q7 edge connector and provides general-purpose SPI connectivity for customer base-boards. With some minor improvements on integration into our outbound tree - explicitly modelled the SPI flash as 'spiflash' under spi0 [dts: rk3399-puma: explicitly model spi-flash under spi1] - renamed the aliases to spi0 and spi1 to allow easier use of commands and legacy (SPL) infrastructure... i.e. the controllers will be 0 and 1 for 'sf probe', 'sspi', etc. [dts: rk3399-puma: rename aliases to number spi as 0 and 1 for commands] * dts: rk3399-puma: include SPI in the spl-boot-order property Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
2017-03-28 16:48:51 +00:00
status = "okay";
};