2011-11-22 08:51:13 +00:00
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Overview
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=========
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The P3060QDS is a Freescale reference board that hosts the six-core P3060 SOC.
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The P3060 Processor combines six e500mc Power Architecture processor
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cores(1.2GHz) with high-performance datapath acceleration
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architecture(DPAA), CoreNet fabric infrastructure, as well as network
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and peripheral bus interfaces required for networking, telecom/datacom,
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wireless infrastructure, and military/aerospace applications.
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P3060QDS Board Specifications:
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==============================
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Memory subsystem:
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* 2G Bytes UDIMM DDR3(64bit bus) with ECC on
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* 128M Bytes NOR flash single-chip memory
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* 16M Bytes SPI flash
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* 8K Bytes AT24C64 I2C EEPROM for RCW
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Ethernet(Default SERDES 0x19):
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* FM1-dTSEC1: connected to RGMII PHY1 (Vitesse VSC8641 on board,Bottom of dual RJ45)
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* FM1-dTSEC2: connected to RGMII PHY2 (Vitesse VSC8641 on board,Top of dual RJ45)
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* FM1-dTSEC3: connected to SGMII PHY (Vitesse VSC8234 port1 in slot1)
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* FM1-dTSEC4: connected to SGMII PHY (Vitesse VSC8234 port3 in slot1)
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* FM2-dTSEC1: connected to SGMII PHY (Vitesse VSC8234 port0 in slot2)
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* FM2-dTSEC2: connected to SGMII PHY (Vitesse VSC8234 port2 in slot2)
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* FM2-dTSEC3: connected to SGMII PHY (Vitesse VSC8234 port0 in slot1)
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* FM2-dTSEC4: connected to SGMII PHY (Vitesse VSC8234 port2 in slot1)
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PCIe:
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* PCIe1: Lanes A, B, C and D of Bank1 are connected to one x4 PCIe SLOT4
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* PCIe2: Lanes E, F, G and H of Bank1 are connected to one x4 PCIe SLOT3
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RapidIO:
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* sRIO1: Lanes E, F, G and H of Bank1 are connected to sRIO1 (SLOT3)
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* sRIO2: Lanes A, B, C and D of Bank1 are connected to sRIO2 (SLOT4)
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USB:
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* USB1: connected via an external ULPI PHY SMC3315 to a TYPE-A interface
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* USB2: connected via an external ULPI PHY SMC3315 to a TYPE-AB interface
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I2C:
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* I2C1_CH0: EEPROM AT24C64(0x50) RCW, AT24C02(0x51) DDR SPD,
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AT24C02(0x53) DDR SPD, AT24C02(0x57) SystemID, RTC DS3232(0x68)
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* I2C1_CH1: 1588 RiserCard(0x55), HSLB Testport, TempMon
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2011-12-19 11:03:40 +00:00
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ADT7461(0x4C), SerDesMux DS64MB201(0x51/59/5C/5D)
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2011-11-22 08:51:13 +00:00
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* I2C1_CH2: VDD/GVDD/GIDD ZL6100 (0x21/0x22/0x23/0x24/0x40)
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* I2C1_CH3: OCM CFG AT24C02(0x55), OCM IPL AT24C64(0x56)
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* I2C1_CH4: PCIe SLOT1
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* I2C1_CH5: PCIe SLOT2
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* I2C1_CH6: PCIe SLOT3
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* I2C1_CH7: PCIe SLOT4
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* I2C2: NULL
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* I2C3: NULL
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UART:
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* Supports two UARTs up to 115200 bps for console
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Boot from NOR flash
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===================
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1. Build image
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export ARCH=powerpc
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export CROSS_COMPILE=/your_path/gcc-4.5.xx-eglibc-2.11.xx/powerpc-linux-gnu/bin/powerpc-linux-gnu-
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make P3060QDS_config
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make
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2. Program image
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=> tftp 1000000 u-boot.bin
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=> protect off all
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=> erase eff80000 efffffff
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=> cp.b 1000000 eff80000 80000
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3. Program RCW
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=> tftp 1000000 rcw.bin
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=> protect off all
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=> erase e8000000 e801ffff
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=> cp.b 1000000 e8000000 50
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4. Program FMAN Firmware ucode
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=> tftp 1000000 ucode.bin
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=> protect off all
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=> erase ef000000 ef0fffff
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=> cp.b 1000000 ef000000 2000
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5. Change DIP-switch
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RCW Location: SW1[1-5] = 01101 (eLBC 16bit NOR flash)
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Note: 1 stands for 'on', 0 stands for 'off'
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Using the Device Tree Source File
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=================================
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To create the DTB (Device Tree Binary) image file, use a command
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similar to this:
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dtc -O dtb -b 0 -p 1024 p3060qds.dts > p3060qds.dtb
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Or use the following command:
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{linux-2.6}/make p3060qds.dtb ARCH=powerpc
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then the dtb file will be generated under the following directory:
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{linux-2.6}/arch/powerpc/boot/p3060qds.dtb
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Booting Linux
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=============
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Place a linux uImage in the TFTP disk area.
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tftp 1000000 uImage
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tftp 2000000 rootfs.ext2.gz.uboot
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tftp 3000000 p3060rdb.dtb
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bootm 1000000 2000000 3000000
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