mirror of
https://github.com/AsahiLinux/u-boot
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97 lines
2.6 KiB
C
97 lines
2.6 KiB
C
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/*
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* (C) Copyright 2012
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* eInfochips Ltd. <www.einfochips.com>
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* Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
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*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <usb.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/armada100.h>
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#include <asm/arch/utmi-armada100.h>
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static int utmi_phy_init(void)
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{
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struct armd1usb_phy_reg *phy_regs =
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(struct armd1usb_phy_reg *)UTMI_PHY_BASE;
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int timeout;
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setbits_le32(&phy_regs->utmi_ctrl, INPKT_DELAY_SOF | PLL_PWR_UP);
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udelay(1000);
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setbits_le32(&phy_regs->utmi_ctrl, PHY_PWR_UP);
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clrbits_le32(&phy_regs->utmi_pll, PLL_FBDIV_MASK | PLL_REFDIV_MASK);
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setbits_le32(&phy_regs->utmi_pll, N_DIVIDER << PLL_FBDIV | M_DIVIDER);
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setbits_le32(&phy_regs->utmi_tx, PHSEL_VAL << CK60_PHSEL);
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/* Calibrate pll */
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timeout = 10000;
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while (--timeout && ((readl(&phy_regs->utmi_pll) & PLL_READY) == 0))
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;
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if (!timeout)
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return -1;
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udelay(200);
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setbits_le32(&phy_regs->utmi_pll, VCOCAL_START);
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udelay(400);
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clrbits_le32(&phy_regs->utmi_pll, VCOCAL_START);
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udelay(200);
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setbits_le32(&phy_regs->utmi_tx, RCAL_START);
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udelay(400);
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clrbits_le32(&phy_regs->utmi_tx, RCAL_START);
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timeout = 10000;
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while (--timeout && ((readl(&phy_regs->utmi_pll) & PLL_READY) == 0))
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;
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if (!timeout)
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return -1;
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return 0;
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}
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/*
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* Initialize USB host controller's UTMI Physical interface
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*/
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int utmi_init(void)
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{
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struct armd1mpmu_registers *mpmu_regs =
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(struct armd1mpmu_registers *)ARMD1_MPMU_BASE;
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struct armd1apmu_registers *apmu_regs =
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(struct armd1apmu_registers *)ARMD1_APMU_BASE;
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/* Turn on 26Mhz ref clock for UTMI PLL */
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setbits_le32(&mpmu_regs->acgr, APB2_26M_EN | AP_26M);
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/* USB Clock reset */
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writel(USB_SPH_AXICLK_EN, &apmu_regs->usbcrc);
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writel(USB_SPH_AXICLK_EN | USB_SPH_AXI_RST, &apmu_regs->usbcrc);
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/* Initialize UTMI transceiver */
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return utmi_phy_init();
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}
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